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Message-ID: <CABPqkBS5AuZDCa6Ab0O7R93gZeb7VROa+5othsapHqatOjWZrQ@mail.gmail.com>
Date: Mon, 11 May 2015 09:32:33 -0700
From: Stephane Eranian <eranian@...gle.com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: Andi Kleen <andi@...stfloor.org>,
LKML <linux-kernel@...r.kernel.org>,
Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH 9/9] x86, perf: Move PMU ACK after LBR read
On Mon, May 11, 2015 at 9:23 AM, Peter Zijlstra <peterz@...radead.org> wrote:
> On Sun, May 10, 2015 at 12:22:47PM -0700, Andi Kleen wrote:
>> From: Andi Kleen <ak@...ux.intel.com>
>>
>> With Arch Perfmon v4 the PMU ack unfreezes the LBRs. So we need to do
>> the PMU ack after the LBR reading, otherwise the LBRs would be polluted by the
>> PMI handler.
>
> Hmm, we should move these last three patches before the SKL enablement
> patch no, otherwise things will misbehave -- say a bisection lands in
> between.
>
> /me shuffles patches.
>
>> This is a minimal change. In principle the ACK could be moved much later.
>
> Right, so the more complete change would be to use the new and improved
> FREEZE_ON_PMI and reenable both the LBRs and the CTRs with the
> STATUS_RESET MSR, right?
>
> Does it make sense to have a new handle_irq() routine for that?
Were we not already using FREEZE_ON_PMI with LBR (except for one
erratum on HSW)?
It would make sense to me to have an "optimized" and clean handle_irq
for the newer PMU.
We the caveat that any change to the core of it would now have to be done twice.
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