linux-kernel - Re: [PATCH] MIPS64: 48 bit physaddr support in memory maps

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Message-ID: <5553D722.1030205@imgtec.com>
Date:	Wed, 13 May 2015 15:58:42 -0700
From:	Leonid Yegoshin <Leonid.Yegoshin@...tec.com>
To:	David Daney <ddaney.cavm@...il.com>
CC:	<linux-mips@...ux-mips.org>, <linux-kernel@...r.kernel.org>,
	<ralf@...ux-mips.org>
Subject: Re: [PATCH] MIPS64: 48 bit physaddr support in memory maps

On 05/13/2015 02:47 PM, David Daney wrote:
> On 05/13/2015 11:55 AM, Leonid Yegoshin wrote:
>> Originally, it was set to 40bits only but I6400 has 48bits of physaddr.
>>
>
> Why not go to the architectural limit of 59 bits?
>

Because any physaddr should fit PTE and EntryLo register and we also 
need 5 or 7 SW bits in PTE.

Even with fixed PTE bits layout from

     http://patchwork.linux-mips.org/patch/7613/

we need 5 or 7 additional bits, so the real limit is 54. And 54 is 
actually specified as a limit in EntryLo starting from MIPS R2.
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