linux-kernel - Re: [PATCH v5 18/21] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp

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Message-ID: <CANLzEktz7Dqd9nRkGMK-iv--wo_LQM0wen8Qsq+jrvG96oSsfA@mail.gmail.com>
Date:	Wed, 13 May 2015 17:29:28 -0700
From:	Benson Leung <bleung@...omium.org>
To:	Rhyland Klein <rklein@...dia.com>
Cc:	Peter De Schrijver <pdeschrijver@...dia.com>,
	Mike Turquette <mturquette@...aro.org>,
	Stephen Warren <swarren@...dotorg.org>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Thierry Reding <thierry.reding@...il.com>,
	Alexandre Courbot <gnurou@...il.com>,
	Bill Huang <bilhuang@...dia.com>,
	Paul Walmsley <pwalmsley@...dia.com>,
	Jim Lin <jilin@...dia.com>, linux-clk@...r.kernel.org,
	linux-tegra@...r.kernel.org,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 18/21] clk: tegra: pll: Fix _pll_ramp_calc_pll logic
 and _calc_dynamic_ramp_rate

On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein <rklein@...dia.com> wrote:
> This removes the conversion from pdiv to hw, which is already taken
> care of by _get_table_rate before this code is run. This avoids
> incorrectly converting pdiv to hw twice and getting the wrong hw value.
>
> Also set the input_rate in the freq cfg in _calc_dynamic_ramp_rate while
> setting all the other fields.
>
> Signed-off-by: Rhyland Klein <rklein@...dia.com>


Reviewed-by: Benson Leung <bleung@...omium.org>

-- 
Benson Leung
Software Engineer, Chrom* OS
bleung@...omium.org
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