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Message-ID: <CANLzEkvUAhXCCvtdHEfmJGONkzNu_dBHj1UUm6Et93kXV1Mz0g@mail.gmail.com>
Date: Thu, 14 May 2015 12:37:24 -0700
From: Benson Leung <bleung@...omium.org>
To: Rhyland Klein <rklein@...dia.com>
Cc: Peter De Schrijver <pdeschrijver@...dia.com>,
Mike Turquette <mturquette@...aro.org>,
Stephen Warren <swarren@...dotorg.org>,
Stephen Boyd <sboyd@...eaurora.org>,
Thierry Reding <thierry.reding@...il.com>,
Alexandre Courbot <gnurou@...il.com>,
Bill Huang <bilhuang@...dia.com>,
Paul Walmsley <pwalmsley@...dia.com>,
Jim Lin <jilin@...dia.com>, linux-clk@...r.kernel.org,
linux-tegra@...r.kernel.org,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 19/21] clk: tegra: Add Super Gen5 Logic
On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein <rklein@...dia.com> wrote:
> From: Bill Huang <bilhuang@...dia.com>
>
> Super clock divider control and clock source mux of Tegra210 has changed
> a little against prior SoCs, this patch adds Gen5 logic to address those
> differences.
>
> Signed-off-by: Bill Huang <bilhuang@...dia.com>
> ---
> v2:
> - Fixed sclk divider address (0x370 -> 0x2c)
>
> drivers/clk/tegra/Makefile | 1 +
> drivers/clk/tegra/clk-tegra-super-gen5.c | 150 ++++++++++++++++++++++++++++++
> drivers/clk/tegra/clk.h | 3 +
> 3 files changed, 154 insertions(+)
> create mode 100644 drivers/clk/tegra/clk-tegra-super-gen5.c
I've diffed clk-tegra-super-gen5.c and the existing
clk-tegra-super-gen4.c, and there's a lot of code duplication here.
They're the same pair of functions, with several small changes. Since
the idea behind pulling out the super clock initialization into a
common file was to reuse the same init, could we extend the super-gen4
file (rename if you have to) to support both gens instead?
--
Benson Leung
Software Engineer, Chrom* OS
bleung@...omium.org
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