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Message-ID: <CANLzEkuDOZQKK4OGBP_z1eHArXC-du0hHLh9Tnojvmd-SzsZwg@mail.gmail.com>
Date: Thu, 14 May 2015 13:02:56 -0700
From: Benson Leung <bleung@...omium.org>
To: Rhyland Klein <rklein@...dia.com>
Cc: Peter De Schrijver <pdeschrijver@...dia.com>,
Mike Turquette <mturquette@...aro.org>,
Stephen Warren <swarren@...dotorg.org>,
Stephen Boyd <sboyd@...eaurora.org>,
Thierry Reding <thierry.reding@...il.com>,
Alexandre Courbot <gnurou@...il.com>,
Bill Huang <bilhuang@...dia.com>,
Paul Walmsley <pwalmsley@...dia.com>,
Jim Lin <jilin@...dia.com>, linux-clk@...r.kernel.org,
linux-tegra@...r.kernel.org,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Andrew Bresticker <abrestic@...omium.org>
Subject: Re: [PATCH v5 21/21] clk: tegra: pll: Fix issues with rates for VCO PLLs
On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein <rklein@...dia.com> wrote:
> From: Andrew Bresticker <abrestic@...omium.org>
>
> Without this change clk_get_rate would return the final output
> rather than the VCO output as it would factor in the pdiv when
> it shouldn't. This will cause problems for all dividers in the
> subtree of the VCO PLL.
>
> Signed-off-by: Andrew Bresticker <abrestic@...omium.org>
> Signed-off-by: Rhyland Klein <rklein@...dia.com>
Reviewed-by: Benson Leung <bleung@...omium.org>
--
Benson Leung
Software Engineer, Chrom* OS
bleung@...omium.org
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