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Message-ID: <555E55F4.2060500@imgtec.com>
Date: Thu, 21 May 2015 19:02:28 -0300
From: Ezequiel Garcia <ezequiel.garcia@...tec.com>
To: Thomas Gleixner <tglx@...utronix.de>
CC: <linux-kernel@...r.kernel.org>, <linux-mips@...ux-mips.org>,
"Daniel Lezcano" <daniel.lezcano@...aro.org>,
<devicetree@...r.kernel.org>,
"Andrew Bresticker" <abrestic@...omium.org>,
James Hartley <james.hartley@...tec.com>,
James Hogan <james.hogan@...tec.com>,
<Damien.Horsley@...tec.com>, <Govindraj.Raja@...tec.com>
Subject: Re: [PATCH 6/7] clocksource: Add Pistachio clocksource-only driver
On 05/21/2015 07:00 PM, Thomas Gleixner wrote:
> On Thu, 21 May 2015, Ezequiel Garcia wrote:
>> +static cycle_t clocksource_read_cycles(struct clocksource *cs)
>> +{
>> + u32 counter, overflw;
>> + unsigned long flags;
>> +
>> + raw_spin_lock_irqsave(&lock, flags);
>
> Hmm. Is that lock really necessary to read that counter? The
> clocksource is global. And if its actually used for timekeeping, the
> lock can get heavy contended.
>
Yup, it is really (and sadly) necessary. The kernel hangs up completely
without it when the counter is accesed by more than one CPU.
Apparently, those two timer registers overflow and counter must be read
atomically.
>> + overflw = gpt_readl(TIMER_CURRENT_OVERFLOW_VALUE, 0);
>> + counter = gpt_readl(TIMER_CURRENT_VALUE, 0);
>> + raw_spin_unlock_irqrestore(&lock, flags);
>> +
>> + return ~(cycle_t)counter;
>> +}
>
> Thanks,
>
> tglx
>
--
Ezequiel
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