linux-kernel - Re: [RFC PATCH 2/4] x86, mwaitt: introduce mwaitx idle with a configurable timer

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Message-ID: <CALCETrXgeMcC-H-S7Y=mP9cbP057m7a2dDEnACK-fJbz3cRjKw@mail.gmail.com>
Date:	Tue, 26 May 2015 18:01:03 -0700
From:	Andy Lutomirski <luto@...capital.net>
To:	Huang Rui <ray.huang@....com>,
	Thomas Gleixner <tglx@...utronix.de>,
	"Rafael J. Wysocki" <rjw@...ysocki.net>,
	Len Brown <lenb@...nel.org>, Borislav Petkov <bp@...e.de>
Cc:	John Stultz <john.stultz@...aro.org>, Tony Li <tony.li@....com>,
	X86 ML <x86@...nel.org>, Peter Zijlstra <peterz@...radead.org>,
	Aaron Lu <aaron.lu@...el.com>,
	Fengguang Wu <fengguang.wu@...el.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [RFC PATCH 2/4] x86, mwaitt: introduce mwaitx idle with a
 configurable timer

On Wed, May 20, 2015 at 10:48 PM, Andy Lutomirski <luto@...capital.net> wrote:
> On May 20, 2015 6:34 PM, "Andy Lutomirski" <luto@...nel.org> wrote:
>> If we did that *and* we had a non-crappy mwaitx, then we could apply an optimization: when going idle, we could turn off the TSC deadline timer and use mwaitx instead.  This would about an interrupt if the event that wakes us is our timer.
>>
>
> Hey, Intel, want to document your secret "Timed MWAIT" feature?  It
> causes a transition to C0 when the deadline expires (see 4.2.4 of the
> Desktop 4th Generation Intel Core Processor Family Datasheet Volume 1,
> order number 328897-001) and it even has an erratum (HSD63 / BDM32),
> but the instruction itself doesn't appear to be documented.
>

Found more:

https://chromium-review.googlesource.com/#/c/205161/

Oddly, Coreboot seems to have mis-spelled that MSR.  It's
MSR_PKG_CST_CONFIG_CONTROL, and bit 31 isn't defined in the SDM
(unsurprisingly).

--Andy
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