linux-kernel - [tip:perf/core] perf/x86/intel/cqm: Document PQR MSR abuse

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Date:	Wed, 27 May 2015 03:02:55 -0700
From:	tip-bot for Thomas Gleixner <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	peterz@...radead.org, will.auld@...el.com,
	kanaka.d.juvva@...el.com, vikas.shivappa@...ux.intel.com,
	mingo@...nel.org, tglx@...utronix.de,
	torvalds@...ux-foundation.org, linux-kernel@...r.kernel.org,
	matt.fleming@...el.com, hpa@...or.com
Subject: [tip:perf/core] perf/x86/intel/cqm: Document PQR MSR abuse

Commit-ID:  f4d9757ca6f5a2db6919a5b1ab86b8afa16773d0
Gitweb:     http://git.kernel.org/tip/f4d9757ca6f5a2db6919a5b1ab86b8afa16773d0
Author:     Thomas Gleixner <tglx@...utronix.de>
AuthorDate: Tue, 19 May 2015 00:00:50 +0000
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Wed, 27 May 2015 09:17:38 +0200

perf/x86/intel/cqm: Document PQR MSR abuse

The CQM code acts like it owns the PQR MSR completely. That's not true
because only the lower 10 bits are used for CQM. The upper 32 bits are
used for the 'CLass Of Service ID' (CLOSID). Document the abuse. Will be
fixed in a later patch.

Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Acked-by: Matt Fleming <matt.fleming@...el.com>
Cc: Kanaka Juvva <kanaka.d.juvva@...el.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Vikas Shivappa <vikas.shivappa@...ux.intel.com>
Cc: Will Auld <will.auld@...el.com>
Link: http://lkml.kernel.org/r/20150518235149.823214798@linutronix.de
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/kernel/cpu/perf_event_intel_cqm.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_cqm.c b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
index e4d1b8b..572582e 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_cqm.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_cqm.c
@@ -978,7 +978,12 @@ static void intel_cqm_event_start(struct perf_event *event, int mode)
 		WARN_ON_ONCE(state->rmid);
 
 	state->rmid = rmid;
-	wrmsrl(MSR_IA32_PQR_ASSOC, state->rmid);
+	/*
+	 * This is actually wrong, as the upper 32 bit MSR contain the
+	 * closid which is used for configuring the Cache Allocation
+	 * Technology component.
+	 */
+	wrmsr(MSR_IA32_PQR_ASSOC, rmid, 0);
 
 	raw_spin_unlock_irqrestore(&state->lock, flags);
 }
@@ -998,7 +1003,13 @@ static void intel_cqm_event_stop(struct perf_event *event, int mode)
 
 	if (!--state->cnt) {
 		state->rmid = 0;
-		wrmsrl(MSR_IA32_PQR_ASSOC, 0);
+		/*
+		 * This is actually wrong, as the upper 32 bit of the
+		 * MSR contain the closid which is used for
+		 * configuring the Cache Allocation Technology
+		 * component.
+		 */
+		wrmsr(MSR_IA32_PQR_ASSOC, 0, 0);
 	} else {
 		WARN_ON_ONCE(!state->rmid);
 	}
--
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