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Message-ID: <20150607120922.GU28762@mwanda>
Date: Sun, 7 Jun 2015 15:09:22 +0300
From: Dan Carpenter <dan.carpenter@...cle.com>
To: David Decotigny <ddecotig@...il.com>
Cc: Oleg Drokin <oleg.drokin@...el.com>,
Andreas Dilger <andreas.dilger@...el.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
HPDD-discuss@...1.01.org, devel@...verdev.osuosl.org,
linux-kernel@...r.kernel.org, Liang Zhen <liang.zhen@...el.com>,
Peng Tao <bergwolf@...il.com>,
Doug Oucharek <doug.s.oucharek@...el.com>,
Amir Shehata <amir.shehata@...el.com>,
Isaac Huang <he.huang@...el.com>
Subject: Re: [PATCH v2 2/2] staging: rtl8723au: core: remove redundant
endianness conversion
On Sat, Jun 06, 2015 at 05:34:00PM -0700, David Decotigny wrote:
> Source and destination have the same little-endian annotation: this
> patch removes forced conversion from host byte order to little-endian.
The patch seems correct but the changelog is a bit wrong. It will
change it from little endian to host endian but we don't want the dest
to be host endian, we want it to be little endain.
regards,
dan carpenter
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