linux-kernel - Re: [PATCH kernel v12 27/34] powerpc/powernv: Implement multilevel TCE tables

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Date:	Tue, 9 Jun 2015 13:57:16 +1000
From:	David Gibson <david@...son.dropbear.id.au>
To:	Alexey Kardashevskiy <aik@...abs.ru>
Cc:	linuxppc-dev@...ts.ozlabs.org,
	Alex Williamson <alex.williamson@...hat.com>,
	Benjamin Herrenschmidt <benh@...nel.crashing.org>,
	Gavin Shan <gwshan@...ux.vnet.ibm.com>,
	Paul Mackerras <paulus@...ba.org>,
	Wei Yang <weiyang@...ux.vnet.ibm.com>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH kernel v12 27/34] powerpc/powernv: Implement multilevel
 TCE tables

On Fri, Jun 05, 2015 at 04:35:19PM +1000, Alexey Kardashevskiy wrote:
> TCE tables might get too big in case of 4K IOMMU pages and DDW enabled
> on huge guests (hundreds of GB of RAM) so the kernel might be unable to
> allocate contiguous chunk of physical memory to store the TCE table.
> 
> To address this, POWER8 CPU (actually, IODA2) supports multi-level
> TCE tables, up to 5 levels which splits the table into a tree of
> smaller subtables.
> 
> This adds multi-level TCE tables support to
> pnv_pci_ioda2_table_alloc_pages() and pnv_pci_ioda2_table_free_pages()
> helpers.
> 
> Signed-off-by: Alexey Kardashevskiy <aik@...abs.ru>

Reviewed-by: David Gibson <david@...son.dropbear.id.au>

-- 
David Gibson			| I'll have my music baroque, and my code
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