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Message-ID: <alpine.DEB.2.10.1506170919060.32420@vshiva-Udesk>
Date: Wed, 17 Jun 2015 09:23:07 -0700 (PDT)
From: Vikas Shivappa <vikas.shivappa@...el.com>
To: Peter Zijlstra <peterz@...radead.org>
cc: Vikas Shivappa <vikas.shivappa@...el.com>,
Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
linux-kernel@...r.kernel.org, x86@...nel.org, hpa@...or.com,
tglx@...utronix.de, mingo@...nel.org,
Matt Fleming <matt.fleming@...el.com>,
"Juvva, Kanaka D" <kanaka.d.juvva@...el.com>,
"Williamson, Glenn P" <glenn.p.williamson@...el.com>,
"Auld, Will" <will.auld@...el.com>
Subject: Re: [PATCH 10/10] x86/intel_rdt: Intel haswell Cache Allocation
enumeration
On Tue, 16 Jun 2015, Peter Zijlstra wrote:
> On Mon, Jun 15, 2015 at 02:44:32PM -0700, Vikas Shivappa wrote:
>>> Secondly, there's more HSW models:
>>>
>>> case 60: /* 22nm Haswell Core */
>>> case 63: /* 22nm Haswell Server */
>>> case 69: /* 22nm Haswell ULT */
>>> case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
>>>
>>> Is this really only HSW server,
>>
>> Yes , this probe is only targeted at HSW servers as of now.
>
> But do the others have it? What you're targeting this code for is
> irrelevant, if those models have the hardware we should support them.
>
>> or should they all be listed?
>
> If they support it, yes. In any case, be explicit on which models have
> the hardware. IIRC your current Changelog has the words 'certain SKUs'
> in, which is as ambiguous as one can get.
Its a little confusing because the quirks we have to use in the clients or even
the details of those is not public. Hence the linux kernel would only support it
in servers for now. Just checked the latest info again and its the same status
as of now.
As far as servers are concerned , its only supported
in certain SKUs and subSKus and
some require a ucode patch. The probe should takes care of them all..
Hope that answers both the questions.
Thanks,
Vikas
>
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