linux-kernel - Re: [PATCH] clk: at91: pll: fix input range validity check

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Message-ID: <20150618125921.0b807f39@bbrezillon>
Date:	Thu, 18 Jun 2015 12:59:21 +0200
From:	Boris Brezillon <boris.brezillon@...e-electrons.com>
To:	Boris Brezillon <boris.brezillon@...e-electrons.com>
Cc:	Mike Turquette <mturquette@...aro.org>,
	Nicolas Ferre <nicolas.ferre@...el.com>,
	Jean-Christophe Plagniol-Villard <plagnioj@...osoft.com>,
	Alexandre Belloni <alexandre.belloni@...e-electrons.com>,
	Jonas Andersson <jonas@...robit.se>,
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	<stable@...r.kernel.org>, Stephen Boyd <sboyd@...eaurora.org>
Subject: Re: [PATCH] clk: at91: pll: fix input range validity check

On Sun, 29 Mar 2015 03:53:43 +0200
Boris Brezillon <boris.brezillon@...e-electrons.com> wrote:

> The PLL impose a certain input range to work correctly, but it appears that
> this input range does not apply on the input clock (or parent clock) but
> on the input clock after it has passed the PLL divisor.
> Fix the implementation accordingly.

Ping (I was expecting this patch to be part of 4.1 :-/).

> 
> Cc: <stable@...r.kernel.org> # v3.14+
> Signed-off-by: Boris Brezillon <boris.brezillon@...e-electrons.com>
> Reported-by: Jonas Andersson <jonas@...robit.se>
> ---
>  drivers/clk/at91/clk-pll.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
> index 6ec79db..cbbe403 100644
> --- a/drivers/clk/at91/clk-pll.c
> +++ b/drivers/clk/at91/clk-pll.c
> @@ -173,8 +173,7 @@ static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
>  	int i = 0;
>  
>  	/* Check if parent_rate is a valid input rate */
> -	if (parent_rate < characteristics->input.min ||
> -	    parent_rate > characteristics->input.max)
> +	if (parent_rate < characteristics->input.min)
>  		return -ERANGE;
>  
>  	/*
> @@ -187,6 +186,15 @@ static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
>  	if (!mindiv)
>  		mindiv = 1;
>  
> +	if (parent_rate > characteristics->input.max) {
> +		tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
> +		if (tmpdiv > PLL_DIV_MAX)
> +			return -ERANGE;
> +
> +		if (tmpdiv > mindiv)
> +			mindiv = tmpdiv;
> +	}
> +
>  	/*
>  	 * Calculate the maximum divider which is limited by PLL register
>  	 * layout (limited by the MUL or DIV field size).



-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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