linux-kernel - Re: [PATCH v2 2/3] IRQ/Gic-V3: Change arm-gic-its to support the Mbigen interrupt

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Date:	Tue, 23 Jun 2015 11:29:13 +0200 (CEST)
From:	Thomas Gleixner <tglx@...utronix.de>
To:	"majun (F)" <majun258@...wei.com>
cc:	Catalin.Marinas@....com, linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, Will.Deacon@....com,
	mark.rutland@....com, marc.zyngier@....com, jason@...edaemon.net,
	lizefan@...wei.com, huxinwei@...wei.com,
	dingtianhong <dingtianhong@...wei.com>,
	吴云 <wuyun.wu@...wei.com>,
	赵俊化 <zhaojunhua@...ilicon.com>,
	"Liguozhu (Kenneth)" <liguozhu@...ilicon.com>,
	许威 <xuwei5@...ilicon.com>,
	chenwei <wei.chenwei@...ilicon.com>
Subject: Re: [PATCH v2 2/3] IRQ/Gic-V3: Change arm-gic-its to support the
 Mbigen interrupt

On Tue, 23 Jun 2015, majun (F) wrote:
> 在 2015/6/19 7:52, Thomas Gleixner 写道:
> > On Mon, 15 Jun 2015, majun (F) wrote:
> >> 在 2015/6/12 18:48, Thomas Gleixner 写道:
> >>> Can you please provide a proper description of this mbigen chip and
> >>> explain WHY you think that it needs all this special hackery?
> > 
> > You carefully avoided to provide a proper description of this mbigen
> > chip and how it needs to be integrated into the GIC/ITS whatever
> > scenario.
> > 
> Mbigen means Message Based Interrupt Generator.
> Its a kind of interrupt controller collects
> the interrupts from external devices and generate msi interrupt.
> 
> Mbigen is applied to reduce the number of wire connected interrupts.
> 
> As the peripherals increasing, the interrupts lines needed is increasing
> much, especially on the Arm64 server soc.
> 
> Therefore, the interrupt pin in gic is not enought for so many perpherals.
> 
> Mbigen is designed to fix this problem.
> 
> Mbigen chip locates in ITS or outside of ITS.
> 
> The working flow of Mbigen shows as below:
> 
> external devices ------> MBIGEN ------->ITS
> 
> The devices connect to Mbigen chip through wire connecting way.
> Mbigen detects and collectes the interrupts from the these devices.
> 
> Then, Mbigen generats the MBI interrupts by writting the ITS
> Translator register.

So it's nothing else than a non PCI based MSI implementation which
means it can simply use the generic MSI infrastructure and implement a
interrupt domain/chip which implements the MBI specific parts and has
the ITS as its parent domain.

No hackery in ITS and no extra functionality in the core irq code. It
just can use the existing infrastructure. The only extra you need is a
proper way to retrieve the pointer to the ITS domain. Everything else
just falls in place.

Thanks,

	tglx