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Message-ID: <9184A2BB-2852-4B73-B964-881A1491EEA8@caviumnetworks.com>
Date: Thu, 25 Jun 2015 23:19:59 +0000
From: "Chalamarla, Tirumalesh" <Tirumalesh.Chalamarla@...iumnetworks.com>
To: "marc.zyngier@....com" <marc.zyngier@....com>
CC: Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
"Ian Campbell" <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will.deacon@....com>,
Liviu Dudau <liviu.dudau@....com>,
Arnd Bergmann <arnd@...db.de>,
"Sunil Goutham" <sgoutham@...ium.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Tirumalesh Chalamarla <tchalamarla@...ium.com>,
Robert Richter <rrichter@...ium.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [PATCH 2/6] GICv3: Add ITS entry to THUNDER dts
Hi Marc,
Any feed back on this.
Do you want me to submit this as a separate patch?so that it is easy for getting acceptance.
Thanks,
Tirumalesh.
> On Sep 24, 2014, at 8:37 AM, Robert Richter <rric@...nel.org> wrote:
>
> From: Tirumalesh Chalamarla <tchalamarla@...ium.com>
>
> The PCIe host controller uses MSIs provided by GICv3 ITS. Enable it on
> Thunder SoCs by adding an entry to DT.
>
> Signed-off-by: Tirumalesh Chalamarla <tchalamarla@...ium.com>
> Signed-off-by: Robert Richter <rrichter@...ium.com>
> ---
> arch/arm64/boot/dts/thunder-88xx.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/thunder-88xx.dtsi b/arch/arm64/boot/dts/thunder-88xx.dtsi
> index d8c0bdc51882..9cb7cf94284a 100644
> --- a/arch/arm64/boot/dts/thunder-88xx.dtsi
> +++ b/arch/arm64/boot/dts/thunder-88xx.dtsi
> @@ -376,10 +376,19 @@
> gic0: interrupt-controller@...0,00000000 {
> compatible = "arm,gic-v3";
> #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> interrupt-controller;
> reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
> <0x8010 0x80000000 0x0 0x600000>; /* GICR */
> interrupts = <1 9 0xf04>;
> +
> + its: gic-its@...0,00020000 {
> + compatible = "arm,gic-v3-its";
> + msi-controller;
> + reg = <0x8010 0x20000 0x0 0x200000>;
> + };
> };
>
> uaa0: serial@...0,24000000 {
> --
> 2.1.0
>
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