linux-kernel - Re: [PATCH v5 2/2] dma: Add Xilinx AXI Central Direct Memory Access Engine driver support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20150627141858.GV19530@localhost>
Date:	Sat, 27 Jun 2015 19:48:58 +0530
From:	Vinod Koul <vinod.koul@...el.com>
To:	Appana Durga Kedareswara Rao <appana.durga.rao@...inx.com>
Cc:	"dan.j.williams@...el.com" <dan.j.williams@...el.com>,
	Michal Simek <michals@...inx.com>,
	Soren Brinkmann <sorenb@...inx.com>,
	Anirudha Sarangi <anirudh@...inx.com>,
	Punnaiah Choudary Kalluri <punnaia@...inx.com>,
	"dmaengine@...r.kernel.org" <dmaengine@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Srikanth Thokala <sthokal@...inx.com>
Subject: Re: [PATCH v5 2/2] dma: Add Xilinx AXI Central Direct Memory Access
 Engine driver support

On Wed, Jun 24, 2015 at 05:12:12PM +0000, Appana Durga Kedareswara Rao wrote:

Please *fix* you MUA to wrap lines properly

> > > +
> > > +   if (cfg->reset)
> > > +           return xilinx_cdma_chan_reset(chan);
> > Why do you want to reset this externally, that sounds bad to me
> If someone (client driver) want to reset the controller externally. It will be useful right?
And why would they want to do that? There might be some other clients using
other channels, doesnt sound good design to me. What is the motivation
here...

> 
> 
> >
> > > +
> > > +   if (cfg->coalesc <= XILINX_CDMA_COALESCE_MAX) {
> > > +           reg &= ~XILINX_CDMA_XR_COALESCE_MASK;
> > > +           reg |= cfg->coalesc << XILINX_CDMA_COALESCE_SHIFT;
> > > +   }
> > Can you explain what coalesc means here?
> 
> Coalesc means interrupt threshold
> This value is used for setting the interrupt threshold. When IOC (interrupt on complete) interrupt events occur, an internal counter
> Counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.
> This will be useful in case of SG transfer.
IIUC, on IOC controller will count this threshold and then generate
interrupt out?

 
> 
> This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
> 
Thats cute!

-- 
~Vinod
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/