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Date:	Tue, 30 Jun 2015 16:47:06 +0300
From:	Jani Nikula <jani.nikula@...ux.intel.com>
To:	Ander Conselvan de Oliveira 
	<ander.conselvan.de.oliveira@...el.com>
Cc:	Linus Torvalds <torvalds@...ux-foundation.org>,
	Dave Airlie <airlied@...ux.ie>,
	Daniel Vetter <daniel.vetter@...el.com>,
	intel-gfx <intel-gfx@...ts.freedesktop.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	DRI mailing list <dri-devel@...ts.freedesktop.org>,
	Ander Conselvan de Oliveira 
	<ander.conselvan.de.oliveira@...el.com>
Subject: Re: [PATCH] drm/i915: Clear pipe's pll hw state in  hsw_dp_set_ddi_pll_sel()

On Tue, 30 Jun 2015, Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@...el.com> wrote:
> Similarly to what is done for SKL, clear the dpll_hw_state of the pipe
> config in hsw_dp_set_ddi_pll_sel(), since it main contain stale values.
> That can happen if a crtc that was previously driving an HDMI connector
> switches to a DP connector. In that case, the wrpll field was left with
> its old value, leading to warnings like the one below:
>
> [drm:check_crtc_state [i915]] *ERROR* mismatch in dpll_hw_state.wrpll (expected 0xb035061f, found 0x00000000)
> ------------[ cut here ]------------
> WARNING: CPU: 1 PID: 767 at drivers/gpu/drm/i915/intel_display.c:12324 check_crtc_state+0x975/0x10b0 [i915]()
> pipe state doesn't match!
>
> This regression was indroduced in
>
> commit dd3cd74acf12723045a64f1f2c6298ac7b34a5d5
> Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@...el.com>
> Date:   Fri May 15 13:34:29 2015 +0300
>
>     drm/i915: Don't overwrite (e)DP PLL selection on SKL
>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@...el.com>

Reported-by: Linus Torvalds <torvalds@...ux-foundation.org>
Tested-by: Jani Nikula <jani.nikula@...el.com>

> ---
>
> Only compile tested, for the wrpll warning.
>
> Thanks,
> Ander
>
>  drivers/gpu/drm/i915/intel_dp.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4ebfc3a..fbd9ac3 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1147,6 +1147,9 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
>  static void
>  hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
>  {
> +	memset(&pipe_config->dpll_hw_state, 0,
> +	       sizeof(pipe_config->dpll_hw_state));
> +
>  	switch (link_bw) {
>  	case DP_LINK_BW_1_62:
>  		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
> -- 
> 2.1.0
>

-- 
Jani Nikula, Intel Open Source Technology Center
--
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