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Message-ID: <CALCETrXd54pCdENwN1+ppwFBReLy6Tsq=mm2_X-SCQmUdhwUwQ@mail.gmail.com>
Date:	Wed, 1 Jul 2015 10:33:54 -0700
From:	Andy Lutomirski <luto@...capital.net>
To:	"Brown, Len" <len.brown@...el.com>
Cc:	Ingo Molnar <mingo@...nel.org>,
	Prarit Bhargava <prarit@...hat.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"H. Peter Anvin" <hpa@...or.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>, X86 ML <x86@...nel.org>,
	"Chandramouli, Dasaratharaman" 
	<dasaratharaman.chandramouli@...el.com>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>,
	Borislav Petkov <bp@...en8.de>,
	Andy Lutomirski <luto@...nel.org>,
	Denys Vlasenko <dvlasenk@...hat.com>,
	Brian Gerst <brgerst@...il.com>,
	Arnaldo Carvalho de Melo <acme@...radead.org>
Subject: Re: [PATCH] x86, msr: Allow read access to /dev/cpu/X/msr

On Wed, Jul 1, 2015 at 9:38 AM, Brown, Len <len.brown@...el.com> wrote:
> BTW. I've had a discussion w/ LLNL about their needs,
> both for security and performance.  For security, as concluded
> by this thread, a white list is the only way to go.
> I'm thinking a bit-vector of allowed MSR offsets...
> For performance, they absolutely can not afford a system call
> for every single MSR access.

I'm surprised.  On a sane kernel, a syscall is about 120 cycles.  Just
rdmsr to an unoptimized MSR is probably fifty cycles, I'd guess.

Of course, LLNL is probably using NOHZ_FULL, which is currently very,
very slow.  Work is afoot to fix that.

>  Here an ioctl to have the
> msr driver perform a vector of accesses in a single system
> call seems the way to go.  I can prototype both of these
> using turbostat as the customer.

How about preadv?

--Andy
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