linux-kernel - Re: [PATCH v2 0/2] pci: xgene: Add multiple memory ranges support

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Date:	Thu, 9 Jul 2015 14:24:04 -0700
From:	Duc Dang <dhdang@....com>
To:	Arnd Bergmann <arnd@...db.de>
Cc:	Bjorn Helgaas <bhelgaas@...gle.com>,
	Catalin Marinas <catalin.marinas@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Pawel Moll <pawel.moll@....com>,
	Rob Herring <robh+dt@...nel.org>,
	Mark Rutland <mark.rutland@....com>,
	Kumar Gala <galak@...eaurora.org>,
	Will Deacon <will.deacon@....com>,
	"David S. Miller" <davem@...emloft.net>,
	devicetree@...r.kernel.org, linux-pci@...r.kernel.org,
	linux-arm <linux-arm-kernel@...ts.infradead.org>,
	linux-kernel@...r.kernel.org, Tanmay Inamdar <tinamdar@....com>,
	patches <patches@....com>
Subject: Re: [PATCH v2 0/2] pci: xgene: Add multiple memory ranges support

On Thu, Jul 9, 2015 at 4:47 AM, Arnd Bergmann <arnd@...db.de> wrote:
>
> On Monday 06 July 2015 16:28:43 Duc Dang wrote:
> > On Tue, Jun 30, 2015 at 11:22 AM, Duc Dang <dhdang@....com> wrote:
> > > This patch set adds 1 large (up to 64GB) memory window for each PCIe
> > > controller nodes in X-Gene device tree and fix PCIe controller driver
> > > to handle multiple memory ranges correctly. These changes are required
> > > to support PCIe devices that has huge BAR.
> > >
> > > v2 changes:
> > >         1. Separate device-tree changes and driver changes into different
> > >         patches
> > >         2. Explicitly define new large window as 64-bit prefetchable in dts
> > >         3. Use IORESOURCE_PREFETCH flag to determine which PCIe controller
> > >         register to be used to configure the memory ranges.
> > >
> > >  arch/arm64/boot/dts/apm/apm-storm.dtsi | 23 ++++++++++++++---------
> > >  drivers/pci/host/pci-xgene.c           | 12 ++++++++++--
> > >  2 files changed, 24 insertions(+), 11 deletions(-)
> >
> > Hi Arnd, Bjorn,
> >
> > Do you have additional comment on this v2 patch set?
> >
> >
>
> The changes look ok to me now, but I'd mention in the changelog about
> the fact that one of the windows is prefetchable and the other one
> is not, and that only prefetchable BARs are now using the 64-bit
> window.

Thanks, Arnd.

I posted v3 patch to clarify each PCIe node will have 2 memory windows:
1 non-prefetchable 32-bit memory window and
1 prefetchable 64-bit window

>
>         Arnd
> --
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-- 
Regards,
Duc Dang.
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