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Message-ID: <20150714113801.GK19282@twins.programming.kicks-ass.net>
Date: Tue, 14 Jul 2015 13:38:01 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Will Deacon <will.deacon@....com>
Cc: "linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
"Waiman.Long@...com" <Waiman.Long@...com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"paulmck@...ux.vnet.ibm.com" <paulmck@...ux.vnet.ibm.com>
Subject: Re: [PATCH 1/5] atomics: add acquire/release/relaxed variants of
some atomic operations
On Tue, Jul 14, 2015 at 12:31:47PM +0100, Will Deacon wrote:
> #ifndef atomic_add
> #define atomic_add(args...) (void)atomic_add_return_relaxed(args);
>
> It would mean a new architecture only has to define a barrier instruction
> and a handful of relaxed atomics for a bare-minimum atomic.h avoiding
> spinlocks.
Look at include/asm-generic/atomic.h, all you need is a cmpxchg().
We could easily change that to be cmpxchg_relaxed() and a few barriers.
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