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Message-ID: <20150714155500.GQ16213@arm.com>
Date: Tue, 14 Jul 2015 16:55:06 +0100
From: Will Deacon <will.deacon@....com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: "linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
"Waiman.Long@...com" <Waiman.Long@...com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"paulmck@...ux.vnet.ibm.com" <paulmck@...ux.vnet.ibm.com>
Subject: Re: [PATCH 1/5] atomics: add acquire/release/relaxed variants of
some atomic operations
On Tue, Jul 14, 2015 at 12:38:01PM +0100, Peter Zijlstra wrote:
> On Tue, Jul 14, 2015 at 12:31:47PM +0100, Will Deacon wrote:
> > #ifndef atomic_add
> > #define atomic_add(args...) (void)atomic_add_return_relaxed(args);
> >
> > It would mean a new architecture only has to define a barrier instruction
> > and a handful of relaxed atomics for a bare-minimum atomic.h avoiding
> > spinlocks.
>
> Look at include/asm-generic/atomic.h, all you need is a cmpxchg().
>
> We could easily change that to be cmpxchg_relaxed() and a few barriers.
Ok, I'll leave that part for now and implement your original suggestion
as a starting point.
Will
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