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Message-ID: <20150714162955.GR16213@arm.com>
Date: Tue, 14 Jul 2015 17:29:56 +0100
From: Will Deacon <will.deacon@....com>
To: David Daney <ddaney@...iumnetworks.com>
Cc: David Daney <ddaney.cavm@...il.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Catalin Marinas <Catalin.Marinas@....com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Robert Richter <rrichter@...ium.com>,
David Daney <david.daney@...ium.com>
Subject: Re: [PATCH] arm64: Define HAVE_ARCH_PIO_SIZE and related symbols.
On Tue, Jul 14, 2015 at 05:12:57PM +0100, David Daney wrote:
> On 07/14/2015 04:00 AM, Will Deacon wrote:
> > On Mon, Jul 13, 2015 at 10:31:36PM +0100, David Daney wrote:
> >> From: David Daney <david.daney@...ium.com>
> >>
> >> Needed to make pci_iomap() work.
> >
> > Care to elaborate?
> >
>
> I should have explained what I am doing here a little better.
Yeah, thanks.
> Systems based on the Cavium ThunderX processor may have up to 8
> independent PCIe root complexes. The I/O space on each bus occupies an
> independent physical address window.
Hmm, so do you have 64k of I/O space per-bus? That gives 8x256x64k = 128M
IIUC, so not sure what your 32MB is for.
> So, in order to be able to map all of these (semi) contiguously, we need
> a lot more virtual address space than is supplied by the default values
> for all these constants.
>
> The option I chose here was to unconditionally expand the I/O ranges for
> all arm64 systems. If you think this breaks existing systems/drivers, I
> will have to look for other options.
Hmm, but pci_iomap winds up calling __pci_ioport_map, which expands to
ioport_map which just does:
return PCI_IOBASE + (port & IO_SPACE_LIMIT);
so I'm struggling to see what your patch achieves.
Will
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