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Message-Id: <1437140050-23363-1-git-send-email-alexander.shishkin@linux.intel.com>
Date: Fri, 17 Jul 2015 16:34:07 +0300
From: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
To: Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc: Ingo Molnar <mingo@...hat.com>, linux-kernel@...r.kernel.org,
adrian.hunter@...el.com, x86@...nel.org, hpa@...or.com,
acme@...radead.org,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Subject: [PATCH 0/3] perf/x86/intel/pt: Add new packet enables
Hi Peter,
There are new PT packets and handles to enable and configure them in the
new version if Intel Architecture SDM. This series deals with timing
related packets: adds bit definitions, cpuid enumeration and relevant
userspace-visible parts.
The bulk of work, as usual, is in the tooling, which I don't include in
this patchset, since it depends on Adrian's earlier work which is still
bouncing between him and the maintainers, but for the sake of completeness
I pushed it to my github tree [1] and Adrian is also sending it out for
review. So anybody interested in trying the whole thing out can pull it
from my tree.
This time around, however, there is no compile time dependency between
mine and his series, since all the relevant bits are communicated through
sysfs.
[1] https://github.com/virtuoso/linux-perf/commits/intel_pt
Alexander Shishkin (3):
perf/x86/intel/pt: Add new timing packet enables
perf/x86/intel/pt: Add an option to not force PSB+ on every
schedule-in
perf/x86/intel/bts: Set itrace_started in pmu::start to match the new
logic
arch/x86/include/asm/msr-index.h | 8 +++
arch/x86/kernel/cpu/intel_pt.h | 6 +++
arch/x86/kernel/cpu/perf_event.h | 1 +
arch/x86/kernel/cpu/perf_event_intel_bts.c | 1 +
arch/x86/kernel/cpu/perf_event_intel_pt.c | 78 ++++++++++++++++++++++++++++--
kernel/events/core.c | 2 -
6 files changed, 91 insertions(+), 5 deletions(-)
--
2.1.4
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