linux-kernel - Re: [PATCH v9 6/7] staging: add simple-fpga-bus

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Date:	Thu, 23 Jul 2015 22:42:05 -0500
From:	atull <atull@...nsource.altera.com>
To:	Jason Gunthorpe <jgunthorpe@...idianresearch.com>
CC:	Moritz Fischer <moritz.fischer@...us.com>,
	Greg KH <gregkh@...uxfoundation.org>, <hpa@...or.com>,
	Michal Simek <monstr@...str.eu>,
	Michal Simek <michal.simek@...inx.com>,
	<rdunlap@...radead.org>, <mark.rutland@....com>,
	<linux-doc@...r.kernel.org>, <rubini@...dd.com>,
	Pantelis Antoniou <pantelis.antoniou@...sulko.com>,
	<s.trumtrar@...gutronix.de>, <devel@...verdev.osuosl.org>,
	<sameo@...ux.intel.com>, Nicolas Pitre <nico@...aro.org>,
	<ijc+devicetree@...lion.org.uk>, <kyle.teske@...com>,
	Grant Likely <grant.likely@...aro.org>,
	David Brown <davidb@...eaurora.org>,
	Linus Walleij <linus.walleij@...aro.org>, <cesarb@...arb.net>,
	<devicetree@...r.kernel.org>, <jason@...edaemon.net>,
	<pawel.moll@....com>, <iws@...o.caltech.edu>, <broonie@...nel.org>,
	Philip Balister <philip@...ister.org>,
	Petr Cvek <petr.cvek@....cz>, <dinguyen@...nsource.altera.com>,
	<pavel@...x.de>, <linux-kernel@...r.kernel.org>, <balbi@...com>,
	Alan Tull <delicious.quinoa@...il.com>, <robh+dt@...nel.org>,
	Rob Landley <rob@...dley.net>,
	Kumar Gala <galak@...eaurora.org>, <akpm@...ux-foundation.org>,
	<davem@...emloft.net>, <m.chehab@...sung.com>
Subject: Re: [PATCH v9 6/7] staging: add simple-fpga-bus

On Thu, 23 Jul 2015, Jason Gunthorpe wrote:

> On Thu, Jul 23, 2015 at 02:55:52PM -0700, Moritz Fischer wrote:
> > Hi Alan,
> > 
> > I saw that your socfpga driver doesn't support the partial reconfig
> > use case (not a big deal).
> > What I currently do for Zynq is if I'm doing a non-partial reconfig is
> > that I disable input
> > level shifters and assert *all* resets while reprogramming in my FPGA
> > manager .write_init() and .write_complete().
> 
> I do this as well, but it is a bit more complex.. FPGA specific code
> has to run around and ensure all DMA is shut off, then we need to make
> sure no CPU issued AXI transactions can happen, then we can tear down
> the FPGA side.
> 
> If the FPGA is torn down while an AXI op is inprogress things go
> sideways, we have to work to prevent that :)
> 
> This happens almost for free, I use DT and the device model to
> disconnect the drivers. The drivers are careful to synchronously fence
> off in-progress DMA. Then drop the DT nodes associated with the
> FPGA, finally the actual FPGA cells can be reset.

Yes, the kernel gives us this almost for free.  That's what I like
about using DT overlays to control FPGA programming.

> 
> > In a partial reconfiguration situation, would I have separate
> > simple-fpga buses for each of the parts that I swap out, each with
> > it's own reset and bitfile attached?
> 
> I'd think of partial reconfiguration as another nested FPGA. The
> resets and so forth could be attached to soft controllers in the
> unswappable part of the FPGA.
> 
> DT nodes have to surround it in some way...
> 
> Jason
> 

Yes, in this way each PR chunk will need its own reset so it
won't wiggle busses and affect the rest of the system during PR.

I noticed that currently simple-fpga-bus.c holds an exclusive
ref of the fpga manager.  This would keep a 2nd pr from being
able to access the same fpga manager, so I'll have to change
it so that simple-fpga-bus.c will  put the ref before exiting
probe.

Alan
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