lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20150728171316.67bb4351@bbrezillon>
Date:	Tue, 28 Jul 2015 17:13:16 +0200
From:	Boris Brezillon <boris.brezillon@...e-electrons.com>
To:	Boris Brezillon <boris.brezillon@...e-electrons.com>
Cc:	Hans de Goede <hdegoede@...hat.com>,
	Michal Suchanek <hramrach@...il.com>,
	David Woodhouse <dwmw2@...radead.org>,
	Brian Norris <computersforpeace@...il.com>,
	Petros Angelatos <petrosagg@...il.com>,
	linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/2] New NAND chip IDs

On Tue, 28 Jul 2015 17:10:13 +0200
Boris Brezillon <boris.brezillon@...e-electrons.com> wrote:

> Hi Hans,
> 
> On Tue, 28 Jul 2015 16:49:58 +0200
> Hans de Goede <hdegoede@...hat.com> wrote:
> 
> > Hi,
> > 
> > On 07/28/2015 04:29 PM, Michal Suchanek wrote:
> > > Hello,
> > >
> > > the NAND chips on Cubietech boards are not known to Linux.
> > >
> > > I used Petros Angelatos' patch from sunxi experimental tree for one chip and
> > > added another chip.
> > >
> > > I hope it's ok to send both patches to avoid merge conflict.
> > 
> > I do not think that these patches are a good idea, this will lead to an
> > ever growing manual maintained list of ids, and that is not maintainable
> > IMHO.
> > 
> > For Samsung chips we only need the ecc strength and size the rest is already
> > detected on the fly, and I've a patch in my personal tree to get the
> > ecc strengt and size from the nand without needing to have an entry per
> > chip:
> > 
> > https://github.com/jwrdegoede/linux-sunxi/commit/53b335d33232753b7aa70298009158baadf5a6bf
> > 
> > This is IMHO a much better solution.
> 
> Hm, IMHO it's not: the nand ids table also store information about
> supported NAND timings, and maybe we'll have to add new things (like
> the read-retry implementation to use for a specific chip).

Oops, sorry, I didn't look at the patch before answering, and I thought
you were suggesting to put the information inside the DT.
Forget my previous answer.


-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ