linux-kernel - Re: Dealing with the NMI mess

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Date:	Thu, 30 Jul 2015 17:54:31 +0200
From:	Paolo Bonzini <pbonzini@...hat.com>
To:	Andy Lutomirski <luto@...capital.net>, Willy Tarreau <w@....eu>
Cc:	Peter Zijlstra <peterz@...radead.org>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Steven Rostedt <rostedt@...dmis.org>, X86 ML <x86@...nel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Borislav Petkov <bp@...en8.de>,
	Thomas Gleixner <tglx@...utronix.de>,
	Brian Gerst <brgerst@...il.com>
Subject: Re: Dealing with the NMI mess



On 24/07/2015 19:20, Andy Lutomirski wrote:
> > Andy, section 5.8 of the SDM makes me think we could possibly abuse SYSRET
> > to emulate IRET, and then possibly simplify the flags processing. It says
> > that it takes the CPL3 code segment but nowhere it says that the target is
> > validated for effectively being userland, and further it suggests that it
> > doesn't validate anything :
> >
> >   "It is the responsibility of the OS to ensure the descriptors in
> >    the GDT/LDT correspond to the selectors loaded by SYSCALL/SYSRET
> >    (consistent with the base, limit, and attribute values forced by
> >    the instructions)."
> You are an evil bastard.  I seriously doubt that this will work.
> SYSRET goes to CPL3 no matter what.  Also, I don't think you want to
> start poking at MSRs to return.

On Intel the bottom two bits of the selector are forced to 11.  The
pseudocode of SYSRET in the SDM has an explicit

	CS.Selector ← (IA32_STAR[63:48]+ either 0 or 16) OR 3;
	...
	SS.Selector ← (IA32_STAR[63:48]+8) OR 3;

On AMD it's even worse, because you get a weird state with
CS.DPL=CS.RPL=SS.DPL=SS.RPL=0 but still the CPL is 3.  This is seriously
messed up because the CPL is always SS.DPL except in this case.  AMD
even had to add a separate field for the CPL to their VM control block,
just to account for this case.  Intel more sanely uses SS.DPL.

Paolo
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