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Message-ID: <alpine.DEB.2.10.1507301145260.921@vshiva-Udesk>
Date:	Thu, 30 Jul 2015 11:45:34 -0700 (PDT)
From:	Vikas Shivappa <vikas.shivappa@...el.com>
To:	Peter Zijlstra <peterz@...radead.org>
cc:	Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
	linux-kernel@...r.kernel.org, vikas.shivappa@...el.com,
	x86@...nel.org, hpa@...or.com, tglx@...utronix.de,
	mingo@...nel.org, tj@...nel.org, matt.fleming@...el.com,
	will.auld@...el.com, glenn.p.williamson@...el.com,
	kanaka.d.juvva@...el.com
Subject: Re: [PATCH 9/9] x86/intel_rdt: Intel haswell Cache Allocation
 enumeration



On Wed, 29 Jul 2015, Peter Zijlstra wrote:

> On Wed, Jul 01, 2015 at 03:21:10PM -0700, Vikas Shivappa wrote:
>> +	/*
>> +	 * Probe test for Haswell CPUs.
>
> Maybe elucidate and say: Probe for Haswell Server parts.
>
> As said before, probe and test mean roughly the same thing, and the
> model test below makes the general 'Haswell CPUs' false, because there's
> at least 3 other models that are also Haswell.

Will fix,
Thanks,
Vikas

>
>> +	 */
>> +	if (c->x86 == 0x6 && c->x86_model == 0x3f)
>> +		return cache_alloc_hsw_probe();
>> +
>
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