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Date:	Fri, 07 Aug 2015 21:28:05 +0530
From:	Vineet Gupta <vgupta@...opsys.com>
To:	Peter Zijlstra <peterz@...radead.org>
CC:	Oleg Nesterov <oleg@...hat.com>,
	Alexander Viro <viro@...iv.linux.org.uk>,
	linux-fsdevel@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] coredump: Replace opencoded set_mask_bits()

On Friday 07 August 2015 09:15 PM, Peter Zijlstra wrote:
> On Fri, Aug 07, 2015 at 09:05:06PM +0530, Vineet Gupta wrote:
>> On Friday 07 August 2015 08:27 PM, Peter Zijlstra wrote:
>>> On Fri, Aug 07, 2015 at 08:14:03PM +0530, Vineet Gupta wrote:
>>>
>>>>> See, I have such a cmpxchg loop in ARC code - originally from Peter :-)
>>>>> arch/arc/kernel/smp.c. @ipi_data_ptr is NOT atomic_t
>>>>>
>>>>> 	do {
>>>>> 		new = old = ACCESS_ONCE(*ipi_data_ptr);
>>>>> 		new |= 1U << msg;
>>>>> 	} while (cmpxchg(ipi_data_ptr, old, new) != old);
>>>>>
>>> Well, you'll have atomic_or() real soon now.
>>
>> Doesn't help my cause - ipi_data_ptr is not atomic_t - hence my prev question in
>> this thread
> 
> A cast will work :-)
> 

How ? We have

typedef struct {
 int counter;
} atomic_t;

> But yes, ideally everything will be type safe because of those archs
> that cannot have atomic RmW ops like !ARC_HAS_LLSC.

Type safe - how / what ?

> 
> Mixing cmpxchg()/xchg() with regular stores is broken on those.

Right, but how does that relate to this discussion - perhaps I shd stop talking -
long friday already :-)

> 
> Fwiw, you might want to set ARCH_SUPPORTS_ATOMIC_RMW for ARC_HAS_LLSC.
> 

Sure I will !
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