| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <1439502278-7617-1-git-send-email-hali@codeaurora.org> Date: Thu, 13 Aug 2015 17:44:38 -0400 From: Hai Li <hali@...eaurora.org> To: dri-devel@...ts.freedesktop.org Cc: linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org, robdclark@...il.com, Hai Li <hali@...eaurora.org> Subject: [PATCH] rnndb/dsi: Add more bits for DSI PHY More registers and bit fields are added for PHY timings and bitclk source selection. Signed-off-by: Hai Li <hali@...eaurora.org> --- rnndb/dsi/dsi.xml | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi/dsi.xml index 02cfa3b..956f3ff 100644 --- a/rnndb/dsi/dsi.xml +++ b/rnndb/dsi/dsi.xml @@ -217,6 +217,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x00128" name="PHY_RESET"> <bitfield name="RESET" pos="0" type="boolean"/> </reg32> + <reg32 offset="0x0017c" name="T_CLK_PRE_EXTEND"> + <bitfield name="INC_BY_2_BYTECLK" pos="0" type="boolean"/> + </reg32> <reg32 offset="0x001d0" name="RDBK_DATA_CTRL"> <bitfield name="COUNT" low="16" high="23" type="uint"/> <bitfield name="CLR" pos="0" type="boolean"/> @@ -437,7 +440,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x001c4" name="BIST_CTRL_4"/> <reg32 offset="0x001c8" name="BIST_CTRL_5"/> - <reg32 offset="0x001d4" name="GLBL_TEST_CTRL"/> + <reg32 offset="0x001d4" name="GLBL_TEST_CTRL"> + <bitfield name="BITCLK_HS_SEL" pos="0" type="boolean"/> + </reg32> <reg32 offset="0x001dc" name="LDO_CNTRL"/> </domain> @@ -608,7 +613,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> <reg32 offset="0x001c4" name="BIST_CTRL_4"/> <reg32 offset="0x001c8" name="BIST_CTRL_5"/> - <reg32 offset="0x001d4" name="GLBL_TEST_CTRL"/> + <reg32 offset="0x001d4" name="GLBL_TEST_CTRL"> + <bitfield name="BITCLK_HS_SEL" pos="0" type="boolean"/> + </reg32> <reg32 offset="0x001dc" name="LDO_CNTRL"/> </domain> -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists