linux-kernel - Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations

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Message-ID: <alpine.DEB.2.11.1508181846160.3873@nanos>
Date:	Tue, 18 Aug 2015 18:46:51 +0200 (CEST)
From:	Thomas Gleixner <tglx@...utronix.de>
To:	Tim Chen <tim.c.chen@...ux.intel.com>
cc:	Dave Hansen <dave.hansen@...el.com>,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>,
	Herbert Xu <herbert@...dor.apana.org.au>,
	Chandramouli Narayanan <mouli@...ux.intel.com>, x86@...nel.org,
	linux-kernel@...r.kernel.org, Borislav Petkov <bp@...e.de>,
	mouli_7982@...oo.com
Subject: Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions
 implementations

On Mon, 17 Aug 2015, Tim Chen wrote:
> Signed-off-by: Chandramouli Narayanan <mouli@...ux.intel.com>
> Signed-off-by: Tim Chen <tim.c.chen@...ux.intel.com>

And now the question who authored this complex one liner ....

> ---
>  arch/x86/include/asm/cpufeature.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index 3d6606f..a94f83d 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -239,6 +239,7 @@
>  #define X86_FEATURE_AVX512PF	( 9*32+26) /* AVX-512 Prefetch */
>  #define X86_FEATURE_AVX512ER	( 9*32+27) /* AVX-512 Exponential and Reciprocal */
>  #define X86_FEATURE_AVX512CD	( 9*32+28) /* AVX-512 Conflict Detection */
> +#define X86_FEATURE_SHA_NI	( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
>  
>  /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
>  #define X86_FEATURE_XSAVEOPT	(10*32+ 0) /* XSAVEOPT */
> -- 
> 1.8.3.1
> 
> 
> 
> 
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