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Message-ID: <1439850820.21627.11.camel@schen9-desk2.jf.intel.com>
Date: Mon, 17 Aug 2015 15:33:40 -0700
From: Tim Chen <tim.c.chen@...ux.intel.com>
To: Dave Hansen <dave.hansen@...el.com>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
"H. Peter Anvin" <hpa@...or.com>,
Herbert Xu <herbert@...dor.apana.org.au>,
Chandramouli Narayanan <mouli@...ux.intel.com>, x86@...nel.org,
linux-kernel@...r.kernel.org, Borislav Petkov <bp@...e.de>,
mouli_7982@...oo.com
Subject: Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions
implementations
On Mon, 2015-08-17 at 14:19 -0700, Dave Hansen wrote:
> On 08/17/2015 01:44 PM, Tim Chen wrote:
> > @@ -401,6 +402,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
> > #define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
> > #define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
> > #define cpu_has_bpext boot_cpu_has(X86_FEATURE_BPEXT)
> > +#define cpu_has_sha_ni boot_cpu_has(X86_FEATURE_SHA_NI)
>
> I think we're trying not to add these cpu_has_* macros any more. For
> MPX at least we were encouraged to call cpu_has(X86_FEATURE_*) directly.
>
> In the patch description, it might also be nice to remind folks that
> this will feature will also show up as "sha_ni" in /proc/cpuinfo.
Okay, in that case, I've modified the patch to below:
Tim
--->8---
Subject: [PATCH] sha: Enable cpuid check for Intel SHA extensions
implementations
To: Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, H. Peter Anvin <hpa@...or.com>
Cc: Herbert Xu <herbert@...dor.apana.org.au>, Chandramouli Narayanan <mouli@...ux.intel.com>, x86@...nel.org, linux-kernel@...r.kernel.org
The Intel Secure Hash Algorithm Extensions are designed to improve the performance
of SHA-1 and SHA-256. This patch adds the check for X86_FEATURE_SHA_NI bit.
This will allow the feature to be shown as sha_ni in the /proc/cpuinfo.
The SHA extension programming guide is found in chapter 8 of the Intel
Architecture Instruction Set Extensions Programming reference:
https://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf
Signed-off-by: Chandramouli Narayanan <mouli@...ux.intel.com>
Signed-off-by: Tim Chen <tim.c.chen@...ux.intel.com>
---
arch/x86/include/asm/cpufeature.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 3d6606f..a94f83d 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -239,6 +239,7 @@
#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
+#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */
--
1.8.3.1
--
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