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Message-Id: <1439963147-2592-1-git-send-email-yamada.masahiro@socionext.com>
Date: Wed, 19 Aug 2015 14:45:47 +0900
From: Masahiro Yamada <yamada.masahiro@...ionext.com>
To: arm@...nel.org
Cc: Masahiro Yamada <yamada.masahiro@...ionext.com>,
Russell King <linux@....linux.org.uk>,
devicetree@...r.kernel.org, Kumar Gala <galak@...eaurora.org>,
linux-kernel@...r.kernel.org,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
linux-arm-kernel@...ts.infradead.org
Subject: [PATCH] ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings
says that the bits[15:8] of the 3rd cell of the interrupts property
represents PPI interrupt CPU mask. Because the timer interrupts are
wired to all of the 4 cores, bits[15:8] should be set to 0xf.
Signed-off-by: Masahiro Yamada <yamada.masahiro@...ionext.com>
---
arch/arm/boot/dts/uniphier-proxstream2.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
index ccf795a..4c7b246 100644
--- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
@@ -249,14 +249,14 @@
timer@...00200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
- interrupts = <1 11 0x304>;
+ interrupts = <1 11 0xf04>;
clocks = <&arm_timer_clk>;
};
timer@...00600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x60000600 0x20>;
- interrupts = <1 13 0x304>;
+ interrupts = <1 13 0xf04>;
clocks = <&arm_timer_clk>;
};
--
1.9.1
--
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