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Message-ID: <CAK7LNATCmyO=Ys_cVJ3sox7Dn+qfKAMyxnBAEXVgZN58ApkDEQ@mail.gmail.com>
Date: Wed, 19 Aug 2015 14:50:25 +0900
From: Masahiro Yamada <yamada.masahiro@...ionext.com>
To: arm@...nel.org
Cc: Mark Rutland <mark.rutland@....com>, devicetree@...r.kernel.org,
Russell King <linux@....linux.org.uk>,
Pawel Moll <pawel.moll@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Masahiro Yamada <yamada.masahiro@...ionext.com>,
Rob Herring <robh+dt@...nel.org>,
Kumar Gala <galak@...eaurora.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH] ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
2015-08-19 14:45 GMT+09:00 Masahiro Yamada <yamada.masahiro@...ionext.com>:
> This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings
> says that the bits[15:8] of the 3rd cell of the interrupts property
> represents PPI interrupt CPU mask. Because the timer interrupts are
> wired to all of the 4 cores, bits[15:8] should be set to 0xf.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@...ionext.com>
This has been superseded by v2.
--
Best Regards
Masahiro Yamada
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