lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20150911175700.GH18779@x1>
Date:	Fri, 11 Sep 2015 18:57:00 +0100
From:	Lee Jones <lee.jones@...aro.org>
To:	Peter Griffin <peter.griffin@...aro.org>
Cc:	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
	srinivas.kandagatla@...il.com, maxime.coquelin@...com,
	patrice.chotard@...com, devicetree@...r.kernel.org,
	Giuseppe Cavallaro <peppe.cavallaro@...com>
Subject: Re: [PATCH 10/11] ARM: DT: STiH407: Add RMII pinctrl support

On Fri, 11 Sep 2015, Peter Griffin wrote:

> This patch adds the RMII pinctrl support for the Synopsys
> MAC on STiH407 SoCs.
> 
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@...com>
> Signed-off-by: Peter Griffin <peter.griffin@...aro.org>
> ---
>  arch/arm/boot/dts/stih407-pinctrl.dtsi | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)

Acked-by: Lee Jones <lee.jones@...aro.org>

> diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
> index 473f2ea..e80cac5 100644
> --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
> @@ -256,6 +256,33 @@
>  						phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
>  					};
>  				};
> +
> +				pinctrl_rmii1: rmii1-0 {
> +					st,pins {
> +						txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
> +						txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
> +						txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
> +						mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
> +						mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
> +						mdint = <&pio1 3 ALT1 IN BYPASS 0>;
> +						rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>;
> +						rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>;
> +						rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>;
> +						rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
> +					};
> +				};
> +
> +				pinctrl_rmii1_phyclk: rmii1_phyclk {
> +					st,pins {
> +						phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
> +					};
> +				};
> +
> +				pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext {
> +					st,pins {
> +						phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>;
> +					};
> +				};
>  			};
>  
>  			pwm1 {

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ