linux-kernel - Re: [PATCH 0/3] MIPS GIC fixes

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Message-ID: <20150922191424.GC29903@NP-P-BURTON>
Date:	Tue, 22 Sep 2015 12:14:24 -0700
From:	Paul Burton <paul.burton@...tec.com>
To:	Thomas Gleixner <tglx@...utronix.de>
CC:	<linux-mips@...ux-mips.org>, <linux-kernel@...r.kernel.org>,
	Jason Cooper <jason@...edaemon.net>,
	James Hogan <james.hogan@...tec.com>,
	Markos Chandras <markos.chandras@...tec.com>,
	Ralf Baechle <ralf@...ux-mips.org>,
	"Marc Zyngier" <marc.zyngier@....com>
Subject: Re: [PATCH 0/3] MIPS GIC fixes

On Tue, Sep 22, 2015 at 09:07:15PM +0200, Thomas Gleixner wrote:
> On Tue, 22 Sep 2015, Paul Burton wrote:
> 
> > This series fixes a couple of problems with the MIPS GIC support,
> > impacting systems with the 64 bit CM3 and those with multithreading and
> > non-contiguous numbering for VP(E)s across cores.
> > 
> > Paul Burton (3):
> >   MIPS: CM: provide a function to map from CPU to VP ID
> >   irqchip: mips-gic: convert CPU numbers to VP IDs
> >   irqchip: mips-gic: fix pending & mask reads for MIPS64 with 32b GIC
> 
> I assume that's a bugfix scheduled for 4.3.
> 
> Ralf, if so, please ship it through the MIPS tree with my Acked-by for
> the irqchip parts.
> 
> Thanks,
> 
> 	tglx

Hi Thomas,

These are fixes but to the best of my knowledge the only currently
supported system it would break is multicore I6400 on Malta, which only
exists in emulation at the moment. So it's probably not a huge deal to
get this into v4.3. If it's easy though, absolutely go ahead :)

I'll aim to be clearer when submitting future fixes about where they
apply.

Thanks,
    Paul
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