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Message-ID: <20150922182902.GO7356@arm.com>
Date: Tue, 22 Sep 2015 19:29:02 +0100
From: Will Deacon <will.deacon@....com>
To: Robert Richter <rric@...nel.org>
Cc: Catalin Marinas <Catalin.Marinas@....com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Tirumalesh Chalamarla <tchalamarla@...ium.com>,
Robert Richter <rrichter@...ium.com>
Subject: Re: [PATCH] arm64: Increase the max granular size
On Tue, Sep 22, 2015 at 06:59:48PM +0100, Robert Richter wrote:
> From: Tirumalesh Chalamarla <tchalamarla@...ium.com>
>
> Increase the standard cacheline size to avoid having locks in the same
> cacheline.
>
> Cavium's ThunderX core implements cache lines of 128 byte size. With
> current granulare size of 64 bytes (L1_CACHE_SHIFT=6) two locks could
> share the same cache line leading a performance degradation.
> Increasing the size fixes that.
Do you have an example of that happening?
> Increasing the size has no negative impact to cache invalidation on
> systems with a smaller cache line. There is an impact on memory usage,
> but that's not too important for arm64 use cases.
Do you have any before/after numbers to show the impact of this change
on other supported SoCs?
Will
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