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Message-ID: <1442947373-13345-5-git-send-email-paul.burton@imgtec.com>
Date: Tue, 22 Sep 2015 11:42:51 -0700
From: Paul Burton <paul.burton@...tec.com>
To: <linux-mips@...ux-mips.org>
CC: Paul Burton <paul.burton@...tec.com>,
"Steven J. Hill" <Steven.Hill@...tec.com>,
"Maciej W. Rozycki" <macro@...ux-mips.org>,
<linux-kernel@...r.kernel.org>,
James Hogan <james.hogan@...tec.com>,
"Markos Chandras" <markos.chandras@...tec.com>,
Ralf Baechle <ralf@...ux-mips.org>
Subject: [PATCH 4/6] MIPS: tidy EntryLo bit definitions, add PFN
Tidy up the definition of the EntryLo RI & XI bits using BITS_PER_LONG
rather than #ifdef'ing on CONFIG_64BIT, and add a definition for the
offset to the PFN field for use by a later patch.
Signed-off-by: Paul Burton <paul.burton@...tec.com>
---
arch/mips/include/asm/mipsregs.h | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index d3cd8ea..76dbb38 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -126,15 +126,9 @@
#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
/* MIPS32/64 EntryLo bit definitions */
-#ifdef CONFIG_64BIT
-/* as read by dmfc0 */
-#define MIPS_ENTRYLO_XI (_ULCAST_(1) << 62)
-#define MIPS_ENTRYLO_RI (_ULCAST_(1) << 63)
-#else
-/* as read by mfc0 */
-#define MIPS_ENTRYLO_XI (_ULCAST_(1) << 30)
-#define MIPS_ENTRYLO_RI (_ULCAST_(1) << 31)
-#endif
+#define MIPS_ENTRYLO_PFN_SHIFT 6
+#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
+#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
/*
* Values for PageMask register
--
2.5.3
--
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