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Message-ID: <1443839086.13186.219.camel@otta>
Date: Fri, 02 Oct 2015 21:24:46 -0500
From: Peter Bergner <bergner@...t.ibm.com>
To: Segher Boessenkool <segher@...nel.crashing.org>
Cc: Denis Kirjanov <kda@...ux-powerpc.org>,
"linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
Laura Abbott <labbott@...hat.com>,
Paul Mackerras <paulus@...ba.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: Missing operand for tlbie instruction on Power7
On Fri, 2015-10-02 at 17:00 -0500, Segher Boessenkool wrote:
> On Sat, Oct 03, 2015 at 12:37:35AM +0300, Denis Kirjanov wrote:
> > >> -0: tlbie r4; \
> > >> +0: tlbie r4, 0; \
> > >
> > > This isn't correct. With POWER7 and later (which this compile
> > > is, since it's on LE), the tlbie instruction takes two register
> > > operands:
> > >
> > > tlbie RB, RS
> > >
> > > The tlbie instruction on pre POWER7 cpus had one required register
> > > operand (RB) and an optional second L operand, where if you omitted
> > > it, it was the same as using "0":
> > >
> > > tlbie RB, L
> > >
> > > This is a POWER7 and later build, so your change which adds the "0"
> > > above is really adding r0 for RS. The new tlbie instruction doesn't
> > > treat r0 specially, so you'll be using whatever random bits which
> > > happen to be in r0 which I don't think that is what you want.
> >
> > Ok, than we can just zero out r5 for example and use it in tlbie as RS,
> > right?
>
> That won't assemble _unless_ your assembler is in POWER7 mode. It also
> won't do the right thing at run time on older machines.
Correct, getting this to work on both pre-power7 and power7 and later
is tricky. One really horrible hack would be to do:
li r0,0
tlbie r4,0
On pre-power7, the "0" will be taken as a zero L operand and on
power7 and later, it'll be r0, but with a zero value we loaded in
the insn before. I know, really ugly. :-)
Peter
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