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Date:	Tue, 6 Oct 2015 11:06:17 -0700
From:	Stephen Boyd <>
To:	Gabriel Fernandez <>
Cc:	Maxime Coquelin <>,
	Michael Turquette <>,
	Peter Griffin <>,
	Pankaj Dev <>,
	Olivier Bideau <>,
	Geert Uytterhoeven <>,
	Fabian Frederick <>,
	Rob Herring <>,
	Pawel Moll <>,
	Mark Rutland <>,
	Ian Campbell <>,
	Kumar Gala <>,
	Srinivas Kandagatla <>,,,,,
Subject: Re: [PATCH v3 2/4] drivers: clk: st: PLL rate change implementation
 for DVFS

On 10/05, Gabriel Fernandez wrote:
> @@ -452,7 +651,7 @@ static const struct clk_ops st_pll1200c32_ops = {
>  static struct clk * __init clkgen_pll_register(const char *parent_name,
>  				struct clkgen_pll_data	*pll_data,
>  				void __iomem *reg,
> -				const char *clk_name)
> +				const char *clk_name, spinlock_t *lock)

Is there a reason we pass lock here but never use it in this

>  {
>  	struct clkgen_pll *pll;
>  	struct clk *clk;

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