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Message-ID: <20151006180617.GE12338@codeaurora.org>
Date: Tue, 6 Oct 2015 11:06:17 -0700
From: Stephen Boyd <sboyd@...eaurora.org>
To: Gabriel Fernandez <gabriel.fernandez@...aro.org>
Cc: Maxime Coquelin <maxime.coquelin@...com>,
Michael Turquette <mturquette@...libre.com>,
Peter Griffin <peter.griffin@...aro.org>,
Pankaj Dev <pankaj.dev@...com>,
Olivier Bideau <olivier.bideau@...com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Fabian Frederick <fabf@...net.be>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Srinivas Kandagatla <srinivas.kandagatla@...il.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, kernel@...inux.com,
linux-clk@...r.kernel.org
Subject: Re: [PATCH v3 2/4] drivers: clk: st: PLL rate change implementation
for DVFS
On 10/05, Gabriel Fernandez wrote:
> @@ -452,7 +651,7 @@ static const struct clk_ops st_pll1200c32_ops = {
> static struct clk * __init clkgen_pll_register(const char *parent_name,
> struct clkgen_pll_data *pll_data,
> void __iomem *reg,
> - const char *clk_name)
> + const char *clk_name, spinlock_t *lock)
Is there a reason we pass lock here but never use it in this
function?
> {
> struct clkgen_pll *pll;
> struct clk *clk;
--
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