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Message-ID: <CAG374jA9W=u7Cq1tNSu1oWuQD68UM768UwckKU6V9+okGUUx8w@mail.gmail.com>
Date:	Wed, 7 Oct 2015 09:47:50 +0200
From:	Gabriel Fernandez <gabriel.fernandez@...aro.org>
To:	Stephen Boyd <sboyd@...eaurora.org>
Cc:	Maxime Coquelin <maxime.coquelin@...com>,
	Michael Turquette <mturquette@...libre.com>,
	Peter Griffin <peter.griffin@...aro.org>,
	Pankaj Dev <pankaj.dev@...com>,
	Olivier Bideau <olivier.bideau@...com>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Fabian Frederick <fabf@...net.be>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Srinivas Kandagatla <srinivas.kandagatla@...il.com>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"kernel@...inux.com" <kernel@...inux.com>,
	linux-clk@...r.kernel.org
Subject: Re: [PATCH v3 2/4] drivers: clk: st: PLL rate change implementation
 for DVFS

Hi Stephen,

No there is no reason. I will fix it.

Thanks for review.

Best regards

Gabriel

On 6 October 2015 at 20:06, Stephen Boyd <sboyd@...eaurora.org> wrote:
> On 10/05, Gabriel Fernandez wrote:
>> @@ -452,7 +651,7 @@ static const struct clk_ops st_pll1200c32_ops = {
>>  static struct clk * __init clkgen_pll_register(const char *parent_name,
>>                               struct clkgen_pll_data  *pll_data,
>>                               void __iomem *reg,
>> -                             const char *clk_name)
>> +                             const char *clk_name, spinlock_t *lock)
>
> Is there a reason we pass lock here but never use it in this
> function?
>
>>  {
>>       struct clkgen_pll *pll;
>>       struct clk *clk;
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
--
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