linux-kernel - Re: [PATCH] pinctrl: tegra-xusb: Correct lane mux options

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Date:	Fri, 23 Oct 2015 12:56:51 -0600
From:	Stephen Warren <swarren@...dotorg.org>
To:	Jon Hunter <jonathanh@...dia.com>,
	Linus Walleij <linus.walleij@...aro.org>,
	Thierry Reding <thierry.reding@...il.com>
Cc:	Alexandre Courbot <gnurou@...il.com>, linux-gpio@...r.kernel.org,
	linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] pinctrl: tegra-xusb: Correct lane mux options

On 10/16/2015 03:24 AM, Jon Hunter wrote:
> The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the Tegra124
> documentation implies that all functions (pcie, usb3 and sata) can be
> muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However, it has
> been confirmed that this is not the case and the mux'ing options much more
> limited. Unfortunately, the public documentation has not been updated to
> reflect this and so detail the actual mux'ing options here by function:
>
> Function:		Lanes:
> pcie1 x2:		pcie3, pcie4
> pcie1 x4:		pcie1, pcie2, pcie3, pcie4
> pcie2 x1 (option1):	pcie0
> pcie2 x1 (option2):	pcie2
> usb3 port 0:		pcie0
> usb3 port 1 (option 1):	pcie1
> usb3 port 1 (option 2):	sata0
> sata:			sata0

Acked-by: Stephen Warren <swarren@...dia.com>

I didn't check the actual lists of values, but it sounds about right 
from memory.
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