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Message-ID: <20151026033722.GD8036@hr-amur2>
Date: Mon, 26 Oct 2015 11:37:23 +0800
From: Huang Rui <ray.huang@....com>
To: Guenter Roeck <linux@...ck-us.net>, Borislav Petkov <bp@...en8.de>
CC: Borislav Petkov <bp@...e.de>,
Peter Zijlstra <peterz@...radead.org>,
"Jean Delvare" <jdelvare@...e.de>,
Andy Lutomirski <luto@...capital.net>,
"Andreas Herrmann" <herrmann.der.user@...il.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...nel.org>,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
"Len Brown" <lenb@...nel.org>,
John Stultz <john.stultz@...aro.org>,
Fr�d�ric Weisbecker <fweisbec@...il.com>,
<lm-sensors@...sensors.org>, <linux-kernel@...r.kernel.org>,
<x86@...nel.org>,
Andreas Herrmann <herrmann.der.user@...glemail.com>,
Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>,
Fengguang Wu <fengguang.wu@...el.com>,
Aaron Lu <aaron.lu@...el.com>, Tony Li <tony.li@....com>
Subject: Re: [PATCH v2 06/10] hwmon: (fam15h_power) Add ptsc counter value
for accumulated power
On Fri, Oct 23, 2015 at 06:59:19AM -0700, Guenter Roeck wrote:
> On 10/19/2015 07:28 PM, Huang Rui wrote:
> >PTSC is the performance timestamp counter value in a cpu core and the
> >cores in one compute unit have the fixed frequency. So it picks up the
> >performance timestamp counter value of the first core per compute unit
> >to measure the interval for average power per compute unit.
> >
> >Signed-off-by: Huang Rui <ray.huang@....com>
> >Cc: Borislav Petkov <bp@...en8.de>
> >Cc: Guenter Roeck <linux@...ck-us.net>
> >Cc: Peter Zijlstra <peterz@...radead.org>
> >Cc: Ingo Molnar <mingo@...nel.org>
> >---
> > arch/x86/include/asm/msr-index.h | 1 +
> > drivers/hwmon/fam15h_power.c | 5 +++++
> > 2 files changed, 6 insertions(+)
> >
> >diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> >index c1c0a1c..3686eaa 100644
> >--- a/arch/x86/include/asm/msr-index.h
> >+++ b/arch/x86/include/asm/msr-index.h
> >@@ -313,6 +313,7 @@
> > #define MSR_F15H_PERF_CTR 0xc0010201
> > #define MSR_F15H_NB_PERF_CTL 0xc0010240
> > #define MSR_F15H_NB_PERF_CTR 0xc0010241
> >+#define MSR_F15H_PTSC 0xc0010280
> >
> > /* Fam 10h MSRs */
> > #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
> >diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon/fam15h_power.c
> >index 88e4f3e..6321f73 100644
> >--- a/drivers/hwmon/fam15h_power.c
> >+++ b/drivers/hwmon/fam15h_power.c
> >@@ -62,6 +62,8 @@ struct fam15h_power_data {
> > u64 max_cu_acc_power;
> > /* accumulated power of the compute units */
> > u64 cu_acc_power[MAX_CUS];
> >+ /* performance timestamp counter */
> >+ u64 cpu_sw_pwr_ptsc[MAX_CUS];
> > };
> >
> > static ssize_t show_power(struct device *dev,
> >@@ -132,6 +134,9 @@ static void do_read_registers_on_cu(void *_data)
> >
> > WARN_ON(rdmsrl_safe(MSR_F15H_CU_PWR_ACCUMULATOR,
> > &data->cu_acc_power[cu]));
> >+
> >+ WARN_ON(rdmsrl_safe(MSR_F15H_PTSC,
> >+ &data->cpu_sw_pwr_ptsc[cu]));
> > }
>
> I am not really happy with those WARN_ON, or even an error message.
> If the error is seen, it may be persistent.
>
> If an error check is really needed here, it might make more sense to store
> the read error and return it to user space if the respective sysfs attribute
> is read.
>
I am OK with removing WARN_ON here. Boris, if you also agree with it,
I will remove it on V3.
Thanks,
Rui
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