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Message-ID: <CAL_JsqK2twfWzCKucuSLrsD2rL3=ReUXt3uPdFcsf8B0Tg42Lg@mail.gmail.com>
Date: Wed, 28 Oct 2015 18:40:27 -0500
From: Rob Herring <robh+dt@...nel.org>
To: Alan Tull <atull@...nsource.altera.com>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Moritz Fischer <moritz.fischer@...us.com>,
Josh Cartwright <joshc@...com>,
Michal Simek <monstr@...str.eu>,
Michal Simek <michal.simek@...inx.com>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Jonathan Corbet <corbet@....net>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>,
Pantelis Antoniou <pantelis.antoniou@...sulko.com>,
delicious.quinoa@...il.com,
Dinh Nguyen <dinguyen@...nsource.altera.com>
Subject: Re: [PATCH v12 2/6] fpga: add bindings document for simple fpga bus
On Tue, Oct 27, 2015 at 5:09 PM, <atull@...nsource.altera.com> wrote:
> From: Alan Tull <atull@...nsource.altera.com>
>
> New bindings document for simple fpga bus.
>
> Signed-off-by: Alan Tull <atull@...nsource.altera.com>
> ---
> v9: initial version added to this patchset
> v10: s/fpga/FPGA/g
> replace DT overlay example with slightly more complicated example
> move to staging/simple-fpga-bus
> v11: No change in this patch for v11 of the patch set
> v12: Moved out of staging.
> Changed to use FPGA bridges framework instead of resets
> for bridges.
> ---
> .../devicetree/bindings/fpga/simple-fpga-bus.txt | 81 ++++++++++++++++++++
> 1 file changed, 81 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/fpga/simple-fpga-bus.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/simple-fpga-bus.txt b/Documentation/devicetree/bindings/fpga/simple-fpga-bus.txt
> new file mode 100644
> index 0000000..2e742f7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/simple-fpga-bus.txt
> @@ -0,0 +1,81 @@
> +Simple FPGA Bus
> +===============
> +
> +A Simple FPGA Bus is a bus that handles configuring an FPGA and its bridges
> +before populating the devices below its node. All this happens when a device
> +tree overlay is added to the live tree. This document describes that device
> +tree overlay.
> +
> +Required properties:
> +- compatible : should contain "simple-fpga-bus"
> +- #address-cells, #size-cells, ranges: must be present to handle address space
> + mapping for children.
> +
> +Optional properties:
> +- fpga-mgr : should contain a phandle to a FPGA manager.
> +- fpga-firmware : should contain the name of a FPGA image file located on the
> + firmware search path.
Putting firmware filename in DT has come up in other cases recently[1]
and we concluded it should not be in the DT. Maybe the conclusion
would be different here, and if so we should have a common property
here.
> +- partial-reconfig : boolean property should be defined if partial
> + reconfiguration of the FPGA is to be done, otherwise full reconfiguration
> + is done.
> +- fpga-bridges : should contain a list of bridges that the bus will disable
> + before programming the FPGA and then enable after the FPGA has been
> +
> +Example:
> +
> +/dts-v1/;
> +/plugin/;
> +/ {
> + fragment@0 {
> + target-path="/soc";
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + bridge@...f200000 {
> + compatible = "simple-fpga-bus";
> + reg = <0xc0000000 0x20000000>,
> + <0xff200000 0x00200000>;
You have registers for the bus, so therefore it is not simple. I think
the bus or bridge needs a specific compatible
Rob
[1] http://www.spinics.net/lists/devicetree/msg92462.html
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