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Message-ID: <CAAtXAHcQDEhUe7ArZhA8D75=ZsGZD8NsL_nqTNTzd4zVqswkQQ@mail.gmail.com>
Date:	Wed, 28 Oct 2015 13:33:02 -0700
From:	Moritz Fischer <moritz.fischer@...us.com>
To:	Josh Cartwright <joshc@...com>
Cc:	atull <atull@...nsource.altera.com>,
	Greg KH <gregkh@...uxfoundation.org>,
	Michal Simek <monstr@...str.eu>,
	Michal Simek <michal.simek@...inx.com>,
	Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Jonathan Corbet <corbet@....net>, linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org, linux-doc@...r.kernel.org,
	Pantelis Antoniou <pantelis.antoniou@...sulko.com>,
	Alan Tull <delicious.quinoa@...il.com>,
	"dinguyen@...nsource.altera.com" <dinguyen@...nsource.altera.com>
Subject: Re: [PATCH v12 3/6] fpga: add simple-fpga-bus

[..]
> I do not think it's a good fit for the socfpga, or for the lower level
> fpga drivers _in general_.  Nor do I think that the FPGA Bridge
> framework, as written, is a good fit for fpgas in general.

Could you elaborate a bit more on why you feel that way? For all
configurations that I could
create in my mind (even hierarchical) I could come up with a way to
model that using the
proposed architecture in a very natural way. I'm of course aware that
my imagination is limited ;-)

Cheers,

Moritz
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