linux-kernel - Re: [PATCH v7 10/17] phy: Add driver for rockchip Display Port PHY

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <563029C6.5000807@rock-chips.com>
Date:	Wed, 28 Oct 2015 09:49:58 +0800
From:	Yakir Yang <ykk@...k-chips.com>
To:	Heiko Stuebner <heiko@...ech.de>,
	linux-rockchip@...ts.infradead.org
Cc:	Inki Dae <inki.dae@...sung.com>,
	Andrzej Hajda <a.hajda@...sung.com>,
	Joonyoung Shim <jy0922.shim@...sung.com>,
	Seung-Woo Kim <sw0312.kim@...sung.com>,
	Kyungmin Park <kyungmin.park@...sung.com>,
	Jingoo Han <jingoohan1@...il.com>,
	Thierry Reding <treding@...dia.com>,
	Krzysztof Kozlowski <k.kozlowski@...sung.com>,
	Rob Herring <robh+dt@...nel.org>, joe@...ches.com,
	Mark Yao <mark.yao@...k-chips.com>, djkurtz@...omium.org,
	dianders@...omium.org,
	Gustavo Padovan <gustavo.padovan@...labora.co.uk>,
	linux-samsung-soc@...r.kernel.org,
	Russell King <linux@....linux.org.uk>,
	Kishon Vijay Abraham I <kishon@...com>,
	javier@....samsung.com, Kukjin Kim <kgene@...nel.org>,
	robherring2@...il.com, devicetree@...r.kernel.org,
	Pawel Moll <pawel.moll@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Sean Paul <seanpaul@...omium.org>,
	dri-devel@...ts.freedesktop.org,
	linux-arm-kernel@...ts.infradead.org, emil.l.velikov@...il.com,
	linux-kernel@...r.kernel.org, Kumar Gala <galak@...eaurora.org>,
	ajaynumb@...il.com, Andy Yan <andy.yan@...k-chips.com>
Subject: Re: [PATCH v7 10/17] phy: Add driver for rockchip Display Port PHY


On 10/28/2015 05:23 AM, Heiko Stuebner wrote:
> Am Samstag, 24. Oktober 2015, 11:06:04 schrieb Yakir Yang:
>> Add phy driver for the Rockchip DisplayPort PHY module. This
>> is required to get DisplayPort working in Rockchip SoCs.
>>
>> Tested-by: Javier Martinez Canillas <javier@....samsung.com>
>> Signed-off-by: Yakir Yang <ykk@...k-chips.com>
>> ---
>> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
>> new file mode 100644
>> index 0000000..4af19af
>> --- /dev/null
>> +++ b/drivers/phy/phy-rockchip-dp.c
>> @@ -0,0 +1,153 @@
>> +/*
>> + * Rockchip DP PHY driver
>> + *
>> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
>> + * Author: Yakir Yang <ykk@@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/clk.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/regmap.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/platform_device.h>
>> +
>> +#define GRF_SOC_CON12                   0x0274
>> +#define GRF_EDP_REF_CLK_SEL_INTER	BIT(4)
>> +#define GRF_EDP_PHY_SIDDQ_WRITE_EN      BIT(21)
>> +#define GRF_EDP_PHY_SIDDQ_ON            0
>> +#define GRF_EDP_PHY_SIDDQ_OFF           BIT(5)
> mixed spacers (tabs and spaces), please use either tabs if you want to
> align stuff or a single space.
>
> Also you're mixing the handling here, for SIDDQ you're defining both the
> actual bit as well as the write-enable bit, but for CLK_SEL_INTR you're
> hard-coding the 16-bit shift down in the code.
>
> You could also just use/copy the HIWORD_MASK macro we use for example
> in the clock controller.
>
>
>> +
>> +struct rockchip_dp_phy {
>> +	struct device  *dev;
>> +	struct regmap  *grf;
>> +	struct clk     *phy_24m;
>> +};
>> +
>> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
>> +{
>> +	struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
>> +	int ret;
>> +
>> +	if (enable) {
>> +		ret = regmap_write(dp->grf, GRF_SOC_CON12,
>> +				   GRF_EDP_PHY_SIDDQ_WRITE_EN |
>> +				   GRF_EDP_PHY_SIDDQ_ON);
>> +		if (ret < 0) {
>> +			dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
>> +			return ret;
>> +		}
>> +
>> +		ret = clk_prepare_enable(dp->phy_24m);
>> +
> unnecessary empty line after clk_prepare_enable
>
>
> with these things fixed,
> Reviewed-by: Heiko Stuebner <heiko@...ech.de>

Oops, thanks

- Yakir

>
> Cheers,
> Heiko
>
>
>


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/