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Message-ID: <20151029082448.2a89c791@bbrezillon>
Date: Thu, 29 Oct 2015 08:24:48 +0100
From: Boris Brezillon <boris.brezillon@...e-electrons.com>
To: Robert Jarzmik <robert.jarzmik@...e.fr>
Cc: Marek Vasut <marex@...x.de>,
Brian Norris <computersforpeace@...il.com>,
linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org,
Ezequiel Garcia <ezequiel.garcia@...e-electrons.com>,
Scott Wood <scottwood@...escale.com>,
Josh Wu <josh.wu@...el.com>,
Kyungmin Park <kyungmin.park@...sung.com>,
Han Xu <han.xu@...escale.com>,
Huang Shijie <shijie.huang@....com>
Subject: Re: [PATCH 1/5] mtd: ofpart: grab device tree node directly from
master device node
Hi Robert,
On Thu, 29 Oct 2015 07:32:33 +0100
Robert Jarzmik <robert.jarzmik@...e.fr> wrote:
> Marek Vasut <marex@...x.de> writes:
>
> >> Isn't there the case of a single NAND controller with 2 identical chips,
> >> each a 8 bit NAND chip, and the controller aggregating them to offer the
> >> OS a single 16-bit NAND chip ?
Honestly, I don't know how this can possibly work, do you have a real
example of that use case.
Here are a few reasons making it impossible:
1/ NAND are accessed using specific command sequences, and those
commands and addresses cycles are sent on through the data bus (AFAIR
only the lower 8bits of a 16bits bus are used for those
command/address cycles), so even if you connect the CLE/ALE/CS/RB pins
on both chips, the one connected on the MSB side of the data bus will
just receive garbage during the command/address sequences, and your
program/read operations won't work
2/ NAND chips can have bad blocks, so even if you were able to address
2 chips (which according to #1 is impossible), you might try to write
on a bad block on the chip connected on the MSB side of the data bus.
3/ There probably are plenty of other reasons why this is not
possible ;-).
Best Regards,
Boris
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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