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Date: Mon, 2 Nov 2015 17:36:25 -0800 From: Davidlohr Bueso <dave@...olabs.net> To: Linus Torvalds <torvalds@...ux-foundation.org> Cc: Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...nel.org>, Thomas Gleixner <tglx@...utronix.de>, "Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, the arch/x86 maintainers <x86@...nel.org>, Davidlohr Bueso <dbueso@...e.de> Subject: Re: [PATCH 3/4] x86,asm: Re-work smp_store_mb() On Mon, 02 Nov 2015, Linus Torvalds wrote: >On Mon, Nov 2, 2015 at 12:15 PM, Davidlohr Bueso <dave@...olabs.net> wrote: >> >> So I ran some experiments on an IvyBridge (2.8GHz) and the cost of XCHG is >> constantly cheaper (by at least half the latency) than MFENCE. While there >> was a decent amount of variation, this difference remained rather constant. > >Mind testing "lock addq $0,0(%rsp)" instead of mfence? That's what we >use on old cpu's without one (ie 32-bit). I'm getting results very close to xchg. >I'm not actually convinced that mfence is necessarily a good idea. I >could easily see it being microcode, for example. Interesting. > >At least on my Haswell, the "lock addq" is pretty much exactly half >the cost of "mfence". Ok, his coincides with my results on IvB. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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