lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Thu, 19 Nov 2015 18:16:42 -0600 From: Matthew McClintock <mmcclint@....qualcomm.com> To: Andy Gross <agross@...eaurora.org>, linux-arm-msm@...r.kernel.org Cc: Matthew McClintock <mmcclint@....qualcomm.com>, linux-kernel@...r.kernel.org, qca-upstream.external@....qualcomm.com Subject: [PATCH v3 6/6] qcom: ipq4019: add acc and saw nodes to bring up secondary cores This adds the required device tree nodes to bring up the secondary cores on the ipq4019 SoC. Signed-off-by: Matthew McClintock <mmcclint@....qualcomm.com> --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index fc73822..e44f5b6 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -27,29 +27,45 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v1"; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; reg = <0x0>; clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v1"; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; reg = <0x1>; clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v1"; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; reg = <0x2>; clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v1"; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; reg = <0x3>; clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; }; }; @@ -92,6 +108,50 @@ interrupts = <0 208 0>; }; + acc0: clock-controller@...8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; + }; + + acc1: clock-controller@...8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; + }; + + acc2: clock-controller@...8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; + }; + + acc3: clock-controller@...8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; + }; + + saw0: regulator@...9000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + + saw1: regulator@...9000 { + compatible = "qcom,saw2"; + reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + + saw2: regulator@...9000 { + compatible = "qcom,saw2"; + reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + + saw3: regulator@...9000 { + compatible = "qcom,saw2"; + reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + serial@...f000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78af000 0x200>; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists