linux-kernel - Re: [PATCH 6/10] watchdog: bcm63xx_wdt: Obtain watchdog clock HZ from "periph" clk

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Date:	Mon, 23 Nov 2015 16:02:22 +0100
From:	Jonas Gorski <jogo@...nwrt.org>
To:	Simon Arlott <simon@...e.lp0.eu>
Cc:	Guenter Roeck <linux@...ck-us.net>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	Ralf Baechle <ralf@...ux-mips.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Jason Cooper <jason@...edaemon.net>,
	Marc Zyngier <marc.zyngier@....com>,
	Kevin Cernekee <cernekee@...il.com>,
	Florian Fainelli <f.fainelli@...il.com>,
	Wim Van Sebroeck <wim@...ana.be>,
	Maxime Bizon <mbizon@...ebox.fr>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	MIPS Mailing List <linux-mips@...ux-mips.org>,
	linux-watchdog@...r.kernel.org, Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>
Subject: Re: [PATCH 6/10] watchdog: bcm63xx_wdt: Obtain watchdog clock HZ from
 "periph" clk

Hi,

On Sun, Nov 22, 2015 at 3:07 PM, Simon Arlott <simon@...e.lp0.eu> wrote:
> Instead of using a fixed clock HZ in the driver, obtain it from the
> "periph" clk that the watchdog timer uses.
>
> Signed-off-by: Simon Arlott <simon@...e.lp0.eu>
> ---
>  drivers/watchdog/bcm63xx_wdt.c | 36 +++++++++++++++++++++++++++++++-----
>  1 file changed, 31 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/watchdog/bcm63xx_wdt.c b/drivers/watchdog/bcm63xx_wdt.c
> index 1d2a501..eb5e551 100644
> --- a/drivers/watchdog/bcm63xx_wdt.c
> +++ b/drivers/watchdog/bcm63xx_wdt.c
> @@ -13,6 +13,7 @@
>
>  #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
>
> +#include <linux/clk.h>
>  #include <linux/errno.h>
>  #include <linux/io.h>
>  #include <linux/kernel.h>
> @@ -32,11 +33,13 @@
>
>  #define PFX KBUILD_MODNAME
>
> -#define WDT_HZ                 50000000                /* Fclk */
> +#define WDT_CLK_NAME           "periph"

@Florian:
Is this correct? The comment for the watchdog in 6358_map_part.h and
earlier claims that the clock is 40 MHz there, but the code uses 50MHz
- is this a bug in the comments or is it a bug taken over from the
original broadcom code? I'm sure that the periph clock being 50 MHz
even on the older chips is correct, else we'd have noticed that in
serial output (where it's also used).


Jonas
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