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Date: Mon, 30 Nov 2015 20:52:55 +0000
From: Simon Arlott <simon@...e.lp0.eu>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>,
Kevin Cernekee <cernekee@...il.com>,
Florian Fainelli <f.fainelli@...il.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Cc: Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-clk@...r.kernel.org, linux-mips@...ux-mips.org,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>
Subject: [PATCH 1/2] clk: Add brcm,bcm63xx-gate-clk device tree binding
Add device tree binding for the BCM63xx's gated clocks.
The BCM63xx contains clocks gated with a register. Clocks are indexed
by bits in the register and are active high. Clock gate bits are
interleaved with other status bits and configurable clocks in the same
register.
Signed-off-by: Simon Arlott <simon@...e.lp0.eu>
---
.../bindings/clock/brcm,bcm63xx-gate-clk.txt | 58 ++++++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt
diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt
new file mode 100644
index 0000000..3f4ead1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/brcm,bcm63xx-gate-clk.txt
@@ -0,0 +1,58 @@
+Broadcom BCM63xx clocks
+
+This binding uses the common clock binding:
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The BCM63xx contains clocks gated with a register. Clocks are indexed
+by bits in the register and are active high. Clock gate bits are
+interleaved with other status bits and configurable clocks in the same
+register.
+
+Required properties:
+- compatible: Should be "brcm,bcm<soc>-gate-clk", "brcm,bcm63xx-gate-clk"
+- #clock-cells: Should be <1>.
+- regmap: The register map phandle
+- offset: Offset in the register map for the reboot register (in bytes)
+- clocks: The external oscillator clock phandle
+
+Example:
+
+periph_clk: periph_clk {
+ compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk";
+ regmap = <&periph_cntl>;
+ offset = <0x4>;
+
+ #clock-cells = <1>;
+ clock-indices =
+ <1>, <2>, <3>, <4>, <5>,
+ <6>, <7>, <8>, <9>, <10>,
+ <11>, <12>, <13>, <14>, <15>,
+ <16>, <17>, <18>, <19>, <20>,
+ <27>, <31>;
+ clock-output-names =
+ "vdsl_qproc", "vdsl_afe", "vdsl", "mips", "wlan_ocp",
+ "dect", "fap0", "fap1", "sar", "robosw",
+ "pcm", "usbd", "usbh", "ipsec", "spi",
+ "hsspi", "pcie", "phymips", "gmac", "nand",
+ "tbus", "robosw250";
+};
+
+timer_clk: timer_clk {
+ compatible = "brcm,bcm63168-gate-clk", "brcm,bcm63xx-gate-clk";
+ regmap = <&timer_cntl>;
+ offset = <0x4>;
+
+ #clock-cells = <1>;
+ clock-indices = <17>, <18>;
+ clock-output-names = "uto_extin", "usb_ref";
+};
+
+ehci0: usb@...02500 {
+ compatible = "brcm,bcm63168-ehci", "brcm,bcm63xx-ehci", "generic-ehci";
+ reg = <0x10002500 0x100>;
+ big-endian;
+ interrupt-parent = <&periph_intc>;
+ interrupts = <10>;
+ clocks = <&periph_clk 13>, <&timer_clk 18>;
+ phys = <&usbh>;
+};
--
2.1.4
--
Simon Arlott
--
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