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Message-ID: <565CB780.3010206@simon.arlott.org.uk>
Date: Mon, 30 Nov 2015 20:54:24 +0000
From: Simon Arlott <simon@...e.lp0.eu>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>,
Kevin Cernekee <cernekee@...il.com>,
Florian Fainelli <f.fainelli@...il.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Cc: Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-clk@...r.kernel.org, linux-mips@...ux-mips.org,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>
Subject: [PATCH 2/2] clk: bcm63xx: Add BCM63xx gated clock support
The BCM63xx contains clocks gated with a register. Clocks are indexed
by bits in the register and are active high. Clock gate bits are
interleaved with other status bits and configurable clocks in the same
register.
Enabled by default for BMIPS_GENERIC.
Signed-off-by: Simon Arlott <simon@...e.lp0.eu>
---
MAINTAINERS | 1 +
drivers/clk/bcm/Kconfig | 8 ++
drivers/clk/bcm/Makefile | 1 +
drivers/clk/bcm/clk-bcm63xx.c | 187 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 197 insertions(+)
create mode 100644 drivers/clk/bcm/clk-bcm63xx.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 29e0589..07613dd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2373,6 +2373,7 @@ F: arch/mips/bmips/*
F: arch/mips/include/asm/mach-bmips/*
F: arch/mips/kernel/*bmips*
F: arch/mips/boot/dts/brcm/bcm*.dts*
+F: drivers/clk/bcm/clk-bcm63*
F: drivers/irqchip/irq-bcm63*
F: drivers/irqchip/irq-bcm7*
F: drivers/irqchip/irq-brcmstb*
diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
index 85260fb..b9c5464 100644
--- a/drivers/clk/bcm/Kconfig
+++ b/drivers/clk/bcm/Kconfig
@@ -14,3 +14,11 @@ config COMMON_CLK_IPROC
help
Enable common clock framework support for Broadcom SoCs
based on the iProc architecture
+
+config CLK_BCM63XX
+ bool "Broadcom BCM63xx clock support"
+ depends on BMIPS_GENERIC
+ depends on COMMON_CLK
+ default y
+ help
+ Enable clock framework support for Broadcom 63xx SoCs
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 3fc9506..4f5f8ce 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.o
obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o
obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o
obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o
+obj-$(CONFIG_CLK_BCM63XX) += clk-bcm63xx.o
diff --git a/drivers/clk/bcm/clk-bcm63xx.c b/drivers/clk/bcm/clk-bcm63xx.c
new file mode 100644
index 0000000..0e8cc06
--- /dev/null
+++ b/drivers/clk/bcm/clk-bcm63xx.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2015 Simon Arlott
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Based on clk-gate.c:
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@...onical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@...aro.org>
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+#include <linux/resource.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+/**
+ * DOC: Basic clock which uses a bit in a regmap to gate and ungate the output
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parent is (un)prepared
+ * enable - clk_enable and clk_disable are functional & control gating
+ * rate - inherits rate from parent. No clk_set_rate support
+ * parent - fixed parent. No clk_set_parent support
+ */
+
+struct clk_bcm63xx {
+ struct clk_hw hw;
+ struct regmap *map;
+ u32 offset;
+ u32 mask;
+};
+
+#define to_clk_bcm63xx(_hw) container_of(_hw, struct clk_bcm63xx, hw)
+
+static int clk_bcm63xx_enable(struct clk_hw *hw)
+{
+ struct clk_bcm63xx *gate = to_clk_bcm63xx(hw);
+
+ return regmap_write_bits(gate->map, gate->offset,
+ gate->mask, gate->mask);
+}
+
+static void clk_bcm63xx_disable(struct clk_hw *hw)
+{
+ struct clk_bcm63xx *gate = to_clk_bcm63xx(hw);
+
+ regmap_write_bits(gate->map, gate->offset,
+ gate->mask, 0);
+}
+
+static int clk_bcm63xx_is_enabled(struct clk_hw *hw)
+{
+ struct clk_bcm63xx *gate = to_clk_bcm63xx(hw);
+ unsigned int val;
+ int ret;
+
+ ret = regmap_read(gate->map, gate->offset, &val);
+ if (ret)
+ return ret;
+
+ val &= gate->mask;
+
+ return val ? 1 : 0;
+}
+
+const struct clk_ops clk_bcm63xx_ops = {
+ .enable = clk_bcm63xx_enable,
+ .disable = clk_bcm63xx_disable,
+ .is_enabled = clk_bcm63xx_is_enabled,
+};
+
+static struct clk * __init of_bcm63xx_clk_register(const char *parent_name,
+ const char *clk_name, struct regmap *map, u32 offset, u32 mask)
+{
+ struct clk_bcm63xx *gate;
+ struct clk_init_data init;
+ struct clk *ret;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = clk_name;
+ init.ops = &clk_bcm63xx_ops;
+ init.flags = CLK_IS_BASIC;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ gate->hw.init = &init;
+ gate->map = map;
+ gate->offset = offset;
+ gate->mask = mask;
+
+ ret = clk_register(NULL, &gate->hw);
+ if (IS_ERR(ret))
+ kfree(gate);
+
+ return ret;
+}
+
+static void __init of_bcm63xx_clk_setup(struct device_node *node)
+{
+ struct clk_onecell_data *clk_data;
+ const char *parent_name = NULL;
+ struct regmap *map;
+ u32 offset;
+ unsigned int clocks = 0;
+ int i;
+
+ clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+ if (!clk_data)
+ return;
+
+ clk_data->clk_num = 32;
+ clk_data->clks = kmalloc_array(clk_data->clk_num,
+ sizeof(*clk_data->clks), GFP_KERNEL);
+
+ for (i = 0; i < clk_data->clk_num; i++)
+ clk_data->clks[i] = ERR_PTR(-ENODEV);
+
+ if (of_clk_get_parent_count(node) > 0)
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ map = syscon_regmap_lookup_by_phandle(node, "regmap");
+ if (IS_ERR(map)) {
+ pr_err("%s: regmap lookup error %ld\n",
+ node->full_name, PTR_ERR(map));
+ goto out;
+ }
+
+ if (of_property_read_u32(node, "offset", &offset)) {
+ pr_err("%s: offset not specified\n", node->full_name);
+ goto out;
+ }
+
+ /* clks[] is sparse, indexed by bit, maximum clocks checked using i */
+ for (i = 0; i < clk_data->clk_num; i++) {
+ u32 bit;
+ const char *clk_name;
+
+ if (of_property_read_u32_index(node, "clock-indices",
+ i, &bit))
+ goto out;
+
+ if (of_property_read_string_index(node, "clock-output-names",
+ i, &clk_name))
+ goto out;
+
+ if (bit >= clk_data->clk_num) {
+ pr_err("%s: clock bit %u out of range\n",
+ node->full_name, bit);
+ continue;
+ }
+
+ if (!IS_ERR(clk_data->clks[bit])) {
+ pr_err("%s: clock bit %u already exists\n",
+ node->full_name, bit);
+ continue;
+ }
+
+ clk_data->clks[bit] = of_bcm63xx_clk_register(parent_name,
+ clk_name, map, offset, BIT(bit));
+ if (!IS_ERR(clk_data->clks[bit]))
+ clocks++;
+ }
+
+out:
+ if (clocks) {
+ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+ pr_info("%s: registered %u clocks\n", node->name, clocks);
+ } else {
+ kfree(clk_data->clks);
+ kfree(clk_data);
+ }
+}
+
+CLK_OF_DECLARE(bcm63xx_clk, "brcm,bcm63xx-gate-clk", of_bcm63xx_clk_setup);
--
2.1.4
--
Simon Arlott
--
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